2002-08-10 04:08:06 +08:00
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//===-- MachineInstr.cpp --------------------------------------------------===//
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2005-04-22 06:36:52 +08:00
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//
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2003-10-21 03:43:21 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 06:36:52 +08:00
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//
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2003-10-21 03:43:21 +08:00
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//===----------------------------------------------------------------------===//
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2004-02-13 12:39:32 +08:00
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//
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// Methods common to all machine instructions.
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//
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2002-08-10 04:08:06 +08:00
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//===----------------------------------------------------------------------===//
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2001-07-21 20:41:50 +08:00
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2001-09-08 01:18:30 +08:00
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#include "llvm/CodeGen/MachineInstr.h"
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2004-02-20 00:17:08 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2002-10-30 08:48:05 +08:00
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#include "llvm/Target/TargetMachine.h"
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2003-01-15 06:00:31 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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2002-10-30 08:58:19 +08:00
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#include "llvm/Target/MRegisterInfo.h"
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2004-09-02 06:55:40 +08:00
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#include "llvm/Support/LeakDetector.h"
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2006-11-29 06:48:48 +08:00
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#include "llvm/Support/Streams.h"
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2006-12-16 06:57:14 +08:00
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#include <ostream>
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2004-02-24 02:38:20 +08:00
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using namespace llvm;
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2003-11-12 06:41:34 +08:00
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2007-12-31 05:56:09 +08:00
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//===----------------------------------------------------------------------===//
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// MachineOperand Implementation
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//===----------------------------------------------------------------------===//
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/// isIdenticalTo - Return true if this operand is identical to the specified
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/// operand.
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bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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if (getType() != Other.getType()) return false;
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switch (getType()) {
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default: assert(0 && "Unrecognized operand type");
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case MachineOperand::MO_Register:
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return getReg() == Other.getReg() && isDef() == Other.isDef() &&
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getSubReg() == Other.getSubReg();
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case MachineOperand::MO_Immediate:
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return getImm() == Other.getImm();
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case MachineOperand::MO_MachineBasicBlock:
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return getMBB() == Other.getMBB();
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case MachineOperand::MO_FrameIndex:
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2007-12-31 07:10:15 +08:00
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return getIndex() == Other.getIndex();
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2007-12-31 05:56:09 +08:00
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case MachineOperand::MO_ConstantPoolIndex:
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2007-12-31 07:10:15 +08:00
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return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
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2007-12-31 05:56:09 +08:00
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case MachineOperand::MO_JumpTableIndex:
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2007-12-31 07:10:15 +08:00
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return getIndex() == Other.getIndex();
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2007-12-31 05:56:09 +08:00
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case MachineOperand::MO_GlobalAddress:
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return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
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case MachineOperand::MO_ExternalSymbol:
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return !strcmp(getSymbolName(), Other.getSymbolName()) &&
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getOffset() == Other.getOffset();
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}
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}
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/// print - Print the specified machine operand.
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///
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void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
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switch (getType()) {
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case MachineOperand::MO_Register:
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if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
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OS << "%reg" << getReg();
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} else {
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// If the instruction is embedded into a basic block, we can find the
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// target
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// info for the instruction.
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if (TM == 0)
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if (const MachineInstr *MI = getParent())
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if (const MachineBasicBlock *MBB = MI->getParent())
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if (const MachineFunction *MF = MBB->getParent())
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TM = &MF->getTarget();
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if (TM)
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OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
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else
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OS << "%mreg" << getReg();
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}
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if (isDef() || isKill() || isDead() || isImplicit()) {
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OS << "<";
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bool NeedComma = false;
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if (isImplicit()) {
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OS << (isDef() ? "imp-def" : "imp-use");
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NeedComma = true;
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} else if (isDef()) {
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OS << "def";
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NeedComma = true;
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}
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if (isKill() || isDead()) {
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if (NeedComma) OS << ",";
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if (isKill()) OS << "kill";
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if (isDead()) OS << "dead";
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}
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OS << ">";
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}
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break;
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case MachineOperand::MO_Immediate:
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OS << getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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OS << "mbb<"
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2007-12-31 07:10:15 +08:00
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<< ((Value*)getMBB()->getBasicBlock())->getName()
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<< "," << (void*)getMBB() << ">";
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2007-12-31 05:56:09 +08:00
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break;
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case MachineOperand::MO_FrameIndex:
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2007-12-31 07:10:15 +08:00
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OS << "<fi#" << getIndex() << ">";
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2007-12-31 05:56:09 +08:00
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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2007-12-31 07:10:15 +08:00
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OS << "<cp#" << getIndex();
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2007-12-31 05:56:09 +08:00
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if (getOffset()) OS << "+" << getOffset();
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OS << ">";
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break;
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case MachineOperand::MO_JumpTableIndex:
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2007-12-31 07:10:15 +08:00
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OS << "<jt#" << getIndex() << ">";
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2007-12-31 05:56:09 +08:00
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)getGlobal())->getName();
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if (getOffset()) OS << "+" << getOffset();
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OS << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << getSymbolName();
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if (getOffset()) OS << "+" << getOffset();
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OS << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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}
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}
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//===----------------------------------------------------------------------===//
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// MachineInstr Implementation
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//===----------------------------------------------------------------------===//
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2006-11-28 07:37:22 +08:00
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/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
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2006-11-30 15:08:44 +08:00
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/// TID NULL and no operands.
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2006-11-28 07:37:22 +08:00
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MachineInstr::MachineInstr()
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2006-11-30 15:08:44 +08:00
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: TID(0), NumImplicitOps(0), parent(0) {
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2004-02-16 15:17:43 +08:00
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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2002-10-29 04:59:49 +08:00
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}
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2006-11-30 15:08:44 +08:00
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void MachineInstr::addImplicitDefUseOperands() {
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if (TID->ImplicitDefs)
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2007-12-30 08:12:25 +08:00
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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2007-12-30 08:41:17 +08:00
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addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
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2006-11-30 15:08:44 +08:00
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if (TID->ImplicitUses)
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2007-12-30 08:12:25 +08:00
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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2007-12-30 08:41:17 +08:00
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addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
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2006-11-14 07:34:06 +08:00
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}
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/// MachineInstr ctor - This constructor create a MachineInstr and add the
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2006-11-28 07:37:22 +08:00
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/// implicit operands. It reserves space for number of operands specified by
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/// TargetInstrDescriptor or the numOperands if it is not zero. (for
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/// instructions with variable number of operands).
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2007-10-13 10:23:01 +08:00
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MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
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2006-11-30 15:08:44 +08:00
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: TID(&tid), NumImplicitOps(0), parent(0) {
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2007-10-13 10:23:01 +08:00
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if (!NoImp && TID->ImplicitDefs)
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2006-11-30 15:08:44 +08:00
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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2006-11-14 07:34:06 +08:00
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NumImplicitOps++;
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2007-10-13 10:23:01 +08:00
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if (!NoImp && TID->ImplicitUses)
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2006-11-30 15:08:44 +08:00
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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2006-11-14 07:34:06 +08:00
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NumImplicitOps++;
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2006-11-30 15:08:44 +08:00
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Operands.reserve(NumImplicitOps + TID->numOperands);
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2007-10-13 10:23:01 +08:00
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if (!NoImp)
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addImplicitDefUseOperands();
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2006-11-14 07:34:06 +08:00
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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2002-10-30 07:19:00 +08:00
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
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/// MachineInstr is created and added to the end of the specified basic block.
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///
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2006-11-28 07:37:22 +08:00
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MachineInstr::MachineInstr(MachineBasicBlock *MBB,
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2006-11-30 15:08:44 +08:00
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const TargetInstrDescriptor &tid)
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: TID(&tid), NumImplicitOps(0), parent(0) {
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2002-10-30 07:19:00 +08:00
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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2006-11-30 15:08:44 +08:00
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if (TID->ImplicitDefs)
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for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
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2006-11-14 07:34:06 +08:00
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NumImplicitOps++;
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2006-11-30 15:08:44 +08:00
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if (TID->ImplicitUses)
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for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
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2006-11-14 07:34:06 +08:00
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NumImplicitOps++;
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2006-11-30 15:08:44 +08:00
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Operands.reserve(NumImplicitOps + TID->numOperands);
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addImplicitDefUseOperands();
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2004-02-16 15:17:43 +08:00
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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2002-10-30 07:19:00 +08:00
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MBB->push_back(this); // Add instruction to end of basic block!
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}
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2004-07-09 22:45:17 +08:00
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/// MachineInstr ctor - Copies MachineInstr arg exactly
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///
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2004-05-24 03:35:12 +08:00
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MachineInstr::MachineInstr(const MachineInstr &MI) {
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2006-11-30 15:08:44 +08:00
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TID = MI.getInstrDescriptor();
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2006-11-16 04:54:29 +08:00
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NumImplicitOps = MI.NumImplicitOps;
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2006-05-05 03:14:44 +08:00
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Operands.reserve(MI.getNumOperands());
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2004-05-24 04:58:02 +08:00
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2004-07-09 22:45:17 +08:00
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// Add operands
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2007-12-30 14:11:04 +08:00
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for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
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2006-05-05 03:14:44 +08:00
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Operands.push_back(MI.getOperand(i));
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2007-12-30 14:11:04 +08:00
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Operands.back().ParentMI = this;
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}
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2004-05-24 11:14:18 +08:00
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2004-07-09 22:45:17 +08:00
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// Set parent, next, and prev to null
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2004-05-24 11:14:18 +08:00
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parent = 0;
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prev = 0;
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next = 0;
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2004-05-24 03:35:12 +08:00
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}
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2004-07-09 22:45:17 +08:00
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MachineInstr::~MachineInstr() {
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2004-02-16 15:17:43 +08:00
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LeakDetector::removeGarbageObject(this);
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2007-12-30 14:11:04 +08:00
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#ifndef NDEBUG
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for (unsigned i = 0, e = Operands.size(); i != e; ++i)
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assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
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#endif
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2004-02-16 15:17:43 +08:00
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}
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2006-11-30 15:08:44 +08:00
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/// getOpcode - Returns the opcode of this MachineInstr.
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///
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2007-09-15 04:08:19 +08:00
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int MachineInstr::getOpcode() const {
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2006-11-30 15:08:44 +08:00
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return TID->Opcode;
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}
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2006-04-18 05:35:41 +08:00
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/// removeFromParent - This method unlinks 'this' from the containing basic
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/// block, and returns it, but does not delete it.
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MachineInstr *MachineInstr::removeFromParent() {
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assert(getParent() && "Not embedded in a basic block!");
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getParent()->remove(this);
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return this;
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}
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2004-02-13 12:39:32 +08:00
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/// OperandComplete - Return true if it's illegal to add a new operand
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///
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2004-02-13 00:09:53 +08:00
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bool MachineInstr::OperandsComplete() const {
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2006-11-30 15:08:44 +08:00
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unsigned short NumOperands = TID->numOperands;
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if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
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2006-11-28 10:25:34 +08:00
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getNumOperands()-NumImplicitOps >= NumOperands)
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2003-05-31 15:39:06 +08:00
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return true; // Broken: we have all the operands of this instruction!
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2002-10-29 04:48:39 +08:00
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return false;
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2001-07-21 20:41:50 +08:00
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}
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2007-05-15 09:26:09 +08:00
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/// getNumExplicitOperands - Returns the number of non-implicit operands.
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///
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unsigned MachineInstr::getNumExplicitOperands() const {
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unsigned NumOperands = TID->numOperands;
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if ((TID->Flags & M_VARIABLE_OPS) == 0)
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return NumOperands;
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for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
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const MachineOperand &MO = getOperand(NumOperands);
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if (!MO.isRegister() || !MO.isImplicit())
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NumOperands++;
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}
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return NumOperands;
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}
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2006-10-21 06:39:59 +08:00
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2007-04-27 03:00:32 +08:00
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/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
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2007-03-27 06:37:45 +08:00
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/// the specific register or -1 if it is not found. It further tightening
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2007-02-23 09:04:26 +08:00
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/// the search criteria to a use that kills the register if isKill is true.
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2007-05-30 02:35:22 +08:00
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int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
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2006-12-06 16:27:42 +08:00
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
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2007-05-30 02:35:22 +08:00
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const MachineOperand &MO = getOperand(i);
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2007-09-15 04:33:02 +08:00
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if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
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2007-02-23 09:04:26 +08:00
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if (!isKill || MO.isKill())
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2007-03-27 06:37:45 +08:00
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return i;
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2007-02-20 05:49:54 +08:00
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}
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2007-03-27 06:37:45 +08:00
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return -1;
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2007-02-20 05:49:54 +08:00
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}
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/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
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/// the specific register or NULL if it is not found.
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MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
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for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
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MachineOperand &MO = getOperand(i);
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2007-09-15 04:33:02 +08:00
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if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
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2006-12-06 16:27:42 +08:00
|
|
|
return &MO;
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
2007-05-15 09:26:09 +08:00
|
|
|
|
2007-05-30 02:35:22 +08:00
|
|
|
/// findFirstPredOperandIdx() - Find the index of the first operand in the
|
|
|
|
/// operand list that is used to represent the predicate. It returns -1 if
|
|
|
|
/// none is found.
|
|
|
|
int MachineInstr::findFirstPredOperandIdx() const {
|
2007-05-15 09:26:09 +08:00
|
|
|
const TargetInstrDescriptor *TID = getInstrDescriptor();
|
2007-05-17 04:56:08 +08:00
|
|
|
if (TID->Flags & M_PREDICABLE) {
|
2007-05-15 09:26:09 +08:00
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
|
|
|
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
|
2007-05-30 02:35:22 +08:00
|
|
|
return i;
|
2007-05-15 09:26:09 +08:00
|
|
|
}
|
|
|
|
|
2007-05-30 02:35:22 +08:00
|
|
|
return -1;
|
2007-05-15 09:26:09 +08:00
|
|
|
}
|
2006-12-06 16:27:42 +08:00
|
|
|
|
2007-10-12 16:50:34 +08:00
|
|
|
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
|
|
|
|
/// to two addr elimination.
|
|
|
|
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
|
|
|
|
const TargetInstrDescriptor *TID = getInstrDescriptor();
|
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO1 = getOperand(i);
|
|
|
|
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
|
|
|
|
for (unsigned j = i+1; j < e; ++j) {
|
|
|
|
const MachineOperand &MO2 = getOperand(j);
|
|
|
|
if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
|
|
|
|
TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-12-06 16:27:42 +08:00
|
|
|
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
|
|
|
|
///
|
|
|
|
void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
|
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
const MachineOperand &MO = MI->getOperand(i);
|
2007-09-15 04:33:02 +08:00
|
|
|
if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
|
2006-12-06 16:27:42 +08:00
|
|
|
continue;
|
|
|
|
for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
|
|
|
|
MachineOperand &MOp = getOperand(j);
|
|
|
|
if (!MOp.isIdenticalTo(MO))
|
|
|
|
continue;
|
|
|
|
if (MO.isKill())
|
|
|
|
MOp.setIsKill();
|
|
|
|
else
|
|
|
|
MOp.setIsDead();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-05-15 09:26:09 +08:00
|
|
|
/// copyPredicates - Copies predicate operand(s) from MI.
|
|
|
|
void MachineInstr::copyPredicates(const MachineInstr *MI) {
|
|
|
|
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
|
2007-05-17 04:56:08 +08:00
|
|
|
if (TID->Flags & M_PREDICABLE) {
|
2007-05-15 09:26:09 +08:00
|
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
|
|
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
|
|
|
|
// Predicated operands must be last operands.
|
2007-12-30 08:41:17 +08:00
|
|
|
addOperand(MI->getOperand(i));
|
2007-05-15 09:26:09 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2004-02-13 12:39:32 +08:00
|
|
|
void MachineInstr::dump() const {
|
2006-12-07 09:30:32 +08:00
|
|
|
cerr << " " << *this;
|
2001-07-21 20:41:50 +08:00
|
|
|
}
|
|
|
|
|
2004-06-25 08:13:11 +08:00
|
|
|
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
|
2007-12-31 05:31:53 +08:00
|
|
|
// Specialize printing if op#0 is definition
|
2002-10-30 09:55:38 +08:00
|
|
|
unsigned StartOp = 0;
|
2007-09-15 04:33:02 +08:00
|
|
|
if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
|
2007-12-31 05:56:09 +08:00
|
|
|
getOperand(0).print(OS, TM);
|
2002-10-30 09:55:38 +08:00
|
|
|
OS << " = ";
|
|
|
|
++StartOp; // Don't print this operand again!
|
|
|
|
}
|
2004-06-25 08:13:11 +08:00
|
|
|
|
2007-12-31 05:31:53 +08:00
|
|
|
OS << getInstrDescriptor()->Name;
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2002-10-30 09:55:38 +08:00
|
|
|
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
|
|
|
|
if (i != StartOp)
|
|
|
|
OS << ",";
|
|
|
|
OS << " ";
|
2007-12-31 05:56:09 +08:00
|
|
|
getOperand(i).print(OS, TM);
|
2002-10-30 08:48:05 +08:00
|
|
|
}
|
2005-04-22 06:36:52 +08:00
|
|
|
|
2002-10-30 08:48:05 +08:00
|
|
|
OS << "\n";
|
|
|
|
}
|
|
|
|
|