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llvm-project/llvm/test/MC/AMDGPU/sop1-err.s

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AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b32 v1, s2
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b32 s1, v0
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b32 s[1:2], s0
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b32 s0, s[1:2]
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b32 s220, s0
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b32 s0, s220
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b64 s1, s[0:1]
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b64 s[0:1], s1
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
// Immediate greater than 32-bits
s_mov_b32 s1, 0xfffffffff
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid immediate: only 32-bit values are legal
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
// Immediate greater than 32-bits
s_mov_b64 s[0:1], 0xfffffffff
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid immediate: only 32-bit values are legal
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
AMDGPU: Fix parsing of 32-bit literals with sign bit set llvm-svn: 251132
2015-10-24 02:07:58 +08:00
s_mov_b64 s[0:1], 0xfffffffff
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid immediate: only 32-bit values are legal
AMDGPU: Fix parsing of 32-bit literals with sign bit set llvm-svn: 251132
2015-10-24 02:07:58 +08:00
s_mov_b64 s[0:1], 0xfffffffff
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid immediate: only 32-bit values are legal
AMDGPU: Fix parsing of 32-bit literals with sign bit set llvm-svn: 251132
2015-10-24 02:07:58 +08:00
s_mov_b64 s[0:1], 0x0000000200000000
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid immediate: only 32-bit values are legal
AMDGPU: Fix parsing of 32-bit literals with sign bit set llvm-svn: 251132
2015-10-24 02:07:58 +08:00
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// FIXME: This shoudl probably say failed to parse.
R600/SI: Initial support for assembler and inline assembly This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
2015-04-08 09:09:26 +08:00
s_mov_b32 s
AMDGPU: Disallow s[102:103] on VI in assembler llvm-svn: 252142
2015-11-05 11:11:27 +08:00
// GCN: error: invalid operand for instruction
// Out of range register
s_mov_b32 s102, 1
// VI: error: invalid operand for instruction
// SI-NOT: error
s_mov_b32 s103, 1
// VI: error: invalid operand for instruction
// SI-NOT: error
s_mov_b64 s[102:103], -1
// VI: error: invalid operand for instruction
// SI-NOT: error