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llvm-project/llvm/lib/Target/Blackfin/Makefile

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Analog Devices Blackfin back-end. Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
2009-08-03 01:32:10 +08:00
##===- lib/Target/Blackfin/Makefile ------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
Stop building RTTI information for *most* llvm libraries. Notable missing ones are libsupport, libsystem and libvmcore. libvmcore is currently blocked on bugpoint, which uses EH. Once it stops using EH, we can switch it off. This #if 0's out 3 unit tests, because gtest requires RTTI information. Suggestions welcome on how to fix this. llvm-svn: 94164
2010-01-22 14:49:46 +08:00
Analog Devices Blackfin back-end. Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
2009-08-03 01:32:10 +08:00
LEVEL = ../../..
LIBRARYNAME = LLVMBlackfinCodeGen
TARGET = Blackfin
# Make sure that tblgen is run, first thing.
Starting to refactor Target to separate out code that's needed to fully describe target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
2011-06-24 09:44:41 +08:00
BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
BlackfinGenInstrNames.inc \
Analog Devices Blackfin back-end. Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
2009-08-03 01:32:10 +08:00
BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
Move Blackfin intrinsics into the Target/Blackfin directory. llvm-svn: 84194
2009-10-16 02:50:52 +08:00
BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
Analog Devices Blackfin back-end. Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
2009-08-03 01:32:10 +08:00
move all the target's asmprinters into the main target. The piece that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056
2010-11-15 02:43:56 +08:00
DIRS = TargetInfo
Analog Devices Blackfin back-end. Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. llvm-svn: 77897
2009-08-03 01:32:10 +08:00
include $(LEVEL)/Makefile.common