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llvm-project/llvm/test/CodeGen/SPARC/fp128.ll

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[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; RUN: llc < %s -march=sparc -mattr=hard-quad-float | FileCheck %s --check-prefix=CHECK --check-prefix=HARD --check-prefix=BE
; RUN: llc < %s -march=sparcel -mattr=hard-quad-float | FileCheck %s --check-prefix=CHECK --check-prefix=HARD --check-prefix=EL
Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that it XFAIL:s also without expensive checks. See https://reviews.llvm.org/D63973
2019-12-03 18:19:16 +08:00
; RUN: llc < %s -march=sparc -mattr=-hard-quad-float -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT --check-prefix=BE
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; RUN: llc < %s -march=sparcel -mattr=-hard-quad-float | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT --check-prefix=EL
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: f128_ops:
; CHECK: ldd
; CHECK: ldd
; CHECK: ldd
; CHECK: ldd
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
; HARD: faddq [[R0:.+]], [[R1:.+]], [[R2:.+]]
; HARD: fsubq [[R2]], [[R3:.+]], [[R4:.+]]
; HARD: fmulq [[R4]], [[R5:.+]], [[R6:.+]]
; HARD: fdivq [[R6]], [[R2]]
; SOFT: call _Q_add
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT: unimp 16
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
; SOFT: call _Q_sub
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT: unimp 16
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
; SOFT: call _Q_mul
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT: unimp 16
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
; SOFT: call _Q_div
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT: unimp 16
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK: std
; CHECK: std
[Sparc] Add long double (f128) instructions to sparc backend. llvm-svn: 189198
2013-08-26 02:30:06 +08:00
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
define void @f128_ops(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a, fp128* byval(fp128) %b, fp128* byval(fp128) %c, fp128* byval(fp128) %d) {
[Sparc] Add long double (f128) instructions to sparc backend. llvm-svn: 189198
2013-08-26 02:30:06 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load fp128, fp128* %a, align 8
%1 = load fp128, fp128* %b, align 8
%2 = load fp128, fp128* %c, align 8
%3 = load fp128, fp128* %d, align 8
[Sparc] Add long double (f128) instructions to sparc backend. llvm-svn: 189198
2013-08-26 02:30:06 +08:00
%4 = fadd fp128 %0, %1
%5 = fsub fp128 %4, %2
%6 = fmul fp128 %5, %3
%7 = fdiv fp128 %6, %4
store fp128 %7, fp128* %scalar.result, align 8
ret void
}
[Sparc] Implement spill and load for long double(f128) registers. llvm-svn: 189768
2013-09-03 02:32:45 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: f128_spill:
; CHECK: std %f{{.+}}, [%[[S0:.+]]]
; CHECK: std %f{{.+}}, [%[[S1:.+]]]
; CHECK-DAG: ldd [%[[S0]]], %f{{.+}}
; CHECK-DAG: ldd [%[[S1]]], %f{{.+}}
; CHECK: jmp {{%[oi]7}}+12
[Sparc] Implement spill and load for long double(f128) registers. llvm-svn: 189768
2013-09-03 02:32:45 +08:00
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
define void @f128_spill(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a) {
[Sparc] Implement spill and load for long double(f128) registers. llvm-svn: 189768
2013-09-03 02:32:45 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load fp128, fp128* %a, align 8
[Sparc] Implement spill and load for long double(f128) registers. llvm-svn: 189768
2013-09-03 02:32:45 +08:00
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
store fp128 %0, fp128* %scalar.result, align 8
ret void
}
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
[Sparc] Fix incorrect MI insertion position for spilling f128. Summary: Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset should be inserted before new created MI for storing even register into memory. So the insertion position should be *StMI instead of II. before fixed: std %f0, [%g1+80] sethi 4, %g1 <<< add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]". sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] after fixed: sethi 4, %g1 add %g1, %sp, %g1 std %f0, [%g1+80] sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60397 llvm-svn: 358042
2019-04-10 09:56:32 +08:00
; CHECK-LABEL: f128_spill_large:
; CHECK: sethi 4, %g1
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: std %f{{.+}}, [%g1]
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: std %f{{.+}}, [%g1+8]
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: ldd [%g1], %f{{.+}}
; CHECK: sethi 4, %g1
; CHECK-NEXT: add %g1, %sp, %g1
; CHECK-NEXT: ldd [%g1+8], %f{{.+}}
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
define void @f128_spill_large(<251 x fp128>* noalias sret(<251 x fp128>) %scalar.result, <251 x fp128>* byval(<251 x fp128>) %a) {
[Sparc] Fix incorrect MI insertion position for spilling f128. Summary: Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset should be inserted before new created MI for storing even register into memory. So the insertion position should be *StMI instead of II. before fixed: std %f0, [%g1+80] sethi 4, %g1 <<< add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]". sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] after fixed: sethi 4, %g1 add %g1, %sp, %g1 std %f0, [%g1+80] sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60397 llvm-svn: 358042
2019-04-10 09:56:32 +08:00
entry:
%0 = load <251 x fp128>, <251 x fp128>* %a, align 8
call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
store <251 x fp128> %0, <251 x fp128>* %scalar.result, align 8
ret void
}
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: f128_compare:
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
; HARD: fcmpq
[Sparc] Do not emit nop after fcmp* instruction with V9. llvm-svn: 192056
2013-10-06 15:06:44 +08:00
; HARD-NEXT: nop
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
; SOFT: _Q_cmp
OpaquePtr: Bulk update tests to use typed byval Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
2020-11-20 23:52:27 +08:00
define i32 @f128_compare(fp128* byval(fp128) %f0, fp128* byval(fp128) %f1, i32 %a, i32 %b) {
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load fp128, fp128* %f0, align 8
%1 = load fp128, fp128* %f1, align 8
[Sparc] Add support for soft long double (fp128). llvm-svn: 189780
2013-09-03 12:11:59 +08:00
%cond = fcmp ult fp128 %0, %1
%ret = select i1 %cond, i32 %a, i32 %b
ret i32 %ret
}
[Sparc] Fix an assertion failure while lowering fcmp on long double. This assertion is triggered because an integer constant is created with wrong type. llvm-svn: 189948
2013-09-04 23:15:20 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: f128_compare2:
; HARD: fcmpq
; HARD: fb{{ule|g}}
[Sparc] Fix an assertion failure while lowering fcmp on long double. This assertion is triggered because an integer constant is created with wrong type. llvm-svn: 189948
2013-09-04 23:15:20 +08:00
; SOFT: _Q_cmp
; SOFT: cmp
OpaquePtr: Bulk update tests to use typed byval Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
2020-11-20 23:52:27 +08:00
define i32 @f128_compare2(fp128* byval(fp128) %f0) {
[Sparc] Fix an assertion failure while lowering fcmp on long double. This assertion is triggered because an integer constant is created with wrong type. llvm-svn: 189948
2013-09-04 23:15:20 +08:00
entry:
[SelectionDAG] Add fcmp UNDEF handling to SelectionDAG::FoldSetCC Second half of PR40800, this patch adds DAG undef handling to fcmp instructions to match the behavior in llvm::ConstantFoldCompareInstruction, this permits constant folding of vector comparisons where some elements had been reduced to UNDEF (by SimplifyDemandedVectorElts etc.). This involves a lot of tweaking to reduced tests as bugpoint loves to reduce fcmp arguments to undef........ Differential Revision: https://reviews.llvm.org/D60006 llvm-svn: 357765
2019-04-05 22:56:21 +08:00
%0 = load fp128, fp128* %f0, align 8
%1 = fcmp ogt fp128 %0, 0xL00000000000000000000000000000000
br i1 %1, label %"5", label %"7"
[Sparc] Fix an assertion failure while lowering fcmp on long double. This assertion is triggered because an integer constant is created with wrong type. llvm-svn: 189948
2013-09-04 23:15:20 +08:00
"5": ; preds = %entry
ret i32 0
"7": ; preds = %entry
ret i32 1
}
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets. llvm-svn: 191154
2013-09-22 07:51:08 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: f128_abs:
; CHECK: ldd [%o0], %f0
; CHECK: ldd [%o0+8], %f2
; BE: fabss %f0, %f0
; EL: fabss %f3, %f3
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets. llvm-svn: 191154
2013-09-22 07:51:08 +08:00
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
define void @f128_abs(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a) {
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets. llvm-svn: 191154
2013-09-22 07:51:08 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load fp128, fp128* %a, align 8
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets. llvm-svn: 191154
2013-09-22 07:51:08 +08:00
%1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
store fp128 %1, fp128* %scalar.result, align 8
ret void
}
declare fp128 @llvm.fabs.f128(fp128) nounwind readonly
[Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand. llvm-svn: 192015
2013-10-05 08:31:41 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: int_to_f128:
[Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand. llvm-svn: 192015
2013-10-05 08:31:41 +08:00
; HARD: fitoq
; SOFT: _Q_itoq
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT: unimp 16
[Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand. llvm-svn: 192015
2013-10-05 08:31:41 +08:00
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
define void @int_to_f128(fp128* noalias sret(fp128) %scalar.result, i32 %i) {
[Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand. llvm-svn: 192015
2013-10-05 08:31:41 +08:00
entry:
%0 = sitofp i32 %i to fp128
store fp128 %0, fp128* %scalar.result, align 8
ret void
}
[Sparc] Use correct alignment while loading/storing fp128 values. llvm-svn: 192023
2013-10-05 10:29:47 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: fp128_unaligned:
; CHECK: ldub
; HARD: faddq
[Sparc] Use correct alignment while loading/storing fp128 values. llvm-svn: 192023
2013-10-05 10:29:47 +08:00
; SOFT: call _Q_add
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT: unimp 16
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK: stb
; CHECK: ret
[Sparc] Use correct alignment while loading/storing fp128 values. llvm-svn: 192023
2013-10-05 10:29:47 +08:00
define void @fp128_unaligned(fp128* %a, fp128* %b, fp128* %c) {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load fp128, fp128* %a, align 1
%1 = load fp128, fp128* %b, align 1
[Sparc] Use correct alignment while loading/storing fp128 values. llvm-svn: 192023
2013-10-05 10:29:47 +08:00
%2 = fadd fp128 %0, %1
store fp128 %2, fp128* %c, align 1
ret void
}
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. llvm-svn: 193947
2013-11-03 16:00:19 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: uint_to_f128:
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. llvm-svn: 193947
2013-11-03 16:00:19 +08:00
; HARD: fdtoq
; SOFT: _Q_utoq
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT: unimp 16
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. llvm-svn: 193947
2013-11-03 16:00:19 +08:00
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
define void @uint_to_f128(fp128* noalias sret(fp128) %scalar.result, i32 %i) {
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. llvm-svn: 193947
2013-11-03 16:00:19 +08:00
entry:
%0 = uitofp i32 %i to fp128
store fp128 %0, fp128* %scalar.result, align 8
ret void
}
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: f128_to_i32:
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. llvm-svn: 193947
2013-11-03 16:00:19 +08:00
; HARD: fqtoi
; HARD: fqtoi
; SOFT: call _Q_qtou
; SOFT: call _Q_qtoi
define i32 @f128_to_i32(fp128* %a, fp128* %b) {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load fp128, fp128* %a, align 8
%1 = load fp128, fp128* %b, align 8
[Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128. llvm-svn: 193947
2013-11-03 16:00:19 +08:00
%2 = fptoui fp128 %0 to i32
%3 = fptosi fp128 %1 to i32
%4 = add i32 %2, %3
ret i32 %4
}
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: test_itoq_qtoi
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
; HARD-DAG: call _Q_lltoq
; HARD-DAG: call _Q_qtoll
; HARD-DAG: fitoq
; HARD-DAG: fqtoi
; SOFT-DAG: call _Q_lltoq
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT-DAG: unimp 16
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
; SOFT-DAG: call _Q_qtoll
; SOFT-DAG: call _Q_itoq
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT-DAG: unimp 16
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
; SOFT-DAG: call _Q_qtoi
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
define void @test_itoq_qtoi(i64 %a, i32 %b, fp128* %c, fp128* %d, i64* %ptr0, fp128* %ptr1) {
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
entry:
%0 = sitofp i64 %a to fp128
store fp128 %0, fp128* %ptr1, align 8
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%cval = load fp128, fp128* %c, align 8
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
%1 = fptosi fp128 %cval to i64
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
store i64 %1, i64* %ptr0, align 8
%2 = sitofp i32 %b to fp128
store fp128 %2, fp128* %ptr1, align 8
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%dval = load fp128, fp128* %d, align 8
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
%3 = fptosi fp128 %dval to i32
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
%4 = bitcast i64* %ptr0 to i32*
store i32 %3, i32* %4, align 8
ret void
}
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: test_utoq_qtou:
; CHECK-DAG: call _Q_ulltoq
; CHECK-DAG: call _Q_qtoull
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; HARD-DAG: fdtoq
; HARD-DAG: fqtoi
; SOFT-DAG: call _Q_utoq
[Sparc] Get sret arg size from CallLoweringInfo.getArgs() Summary: Looking at the callee argument list, as is done now, might not work if the function has been typecasted into one that is expected to return a struct. This change also simplifies the code. The isFP128ABICall() function can be removed as it is no longer needed. The test in fp128.ll has been updated to verify this. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48117 llvm-svn: 340008
2018-08-17 18:40:00 +08:00
; SOFT-DAG: unimp 16
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; SOFT-DAG: call _Q_qtou
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
define void @test_utoq_qtou(i64 %a, i32 %b, fp128* %c, fp128* %d, i64* %ptr0, fp128* %ptr1) {
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
entry:
%0 = uitofp i64 %a to fp128
store fp128 %0, fp128* %ptr1, align 8
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%cval = load fp128, fp128* %c, align 8
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
%1 = fptoui fp128 %cval to i64
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
store i64 %1, i64* %ptr0, align 8
%2 = uitofp i32 %b to fp128
store fp128 %2, fp128* %ptr1, align 8
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%dval = load fp128, fp128* %d, align 8
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
%3 = fptoui fp128 %dval to i32
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
%4 = bitcast i64* %ptr0 to i32*
store i32 %3, i32* %4, align 8
ret void
}
Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
2014-02-28 03:26:29 +08:00
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; CHECK-LABEL: f128_neg:
; CHECK: ldd [%o0], %f0
; CHECK: ldd [%o0+8], %f2
; BE: fnegs %f0, %f0
; EL: fnegs %f3, %f3
Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
2014-02-28 03:26:29 +08:00
OpaquePtr: Bulk update tests to use typed sret
2020-11-21 03:07:11 +08:00
define void @f128_neg(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a) {
Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
2014-02-28 03:26:29 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load fp128, fp128* %a, align 8
Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. llvm-svn: 202422
2014-02-28 03:26:29 +08:00
%1 = fsub fp128 0xL00000000000000008000000000000000, %0
store fp128 %1, fp128* %scalar.result, align 8
ret void
}