2019-09-20 00:44:38 +08:00
|
|
|
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GCN %s
|
|
|
|
|
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,CIVI,GCN %s
|
|
|
|
|
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CI,CIVI,GCN %s
|
2017-02-28 06:15:25 +08:00
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}s_abs_v2i16:
|
|
|
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
|
|
|
|
|
; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
|
2019-06-20 07:37:43 +08:00
|
|
|
; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
|
2017-02-28 06:15:25 +08:00
|
|
|
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
; CIVI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
|
|
|
|
|
; CIVI: s_sub_i32
|
|
|
|
|
; CIVI: s_sub_i32
|
|
|
|
|
; CIVI: s_max_i32
|
|
|
|
|
; CIVI: s_max_i32
|
|
|
|
|
; CIVI: s_add_i32
|
[DAGCombiner] Combine OR as ADD when no common bits are set
Summary:
The DAGCombiner is rewriting (canonicalizing) an ISD::ADD
with no common bits set in the operands as an ISD::OR node.
This could sometimes result in "missing out" on some
combines that normally are performed for ADD. To be more
specific this could happen if we already have rewritten an
ADD into OR, and later (after legalizations or combines)
we expose patterns that could have been optimized if we
had seen the OR as an ADD (e.g. reassociations based on ADD).
To make the DAG combiner less sensitive to if ADD or OR is
used for these "no common bits set" ADD/OR operations we
now apply most of the ADD combines also to an OR operation,
when value tracking indicates that the operands have no
common bits set.
Reviewers: spatel, RKSimon, craig.topper, kparzysz
Reviewed By: spatel
Subscribers: arsenm, rampitec, lebedev.ri, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59758
llvm-svn: 358965
2019-04-23 18:01:08 +08:00
|
|
|
; CIVI-DAG: s_add_i32
|
|
|
|
|
; CIVI-DAG: s_and_b32
|
|
|
|
|
; CIVI-DAG: s_or_b32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @s_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%neg = sub <2 x i16> zeroinitializer, %val
|
|
|
|
|
%cond = icmp sgt <2 x i16> %val, %neg
|
|
|
|
|
%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
|
|
|
|
|
%res2 = add <2 x i16> %res, <i16 2, i16 2>
|
|
|
|
|
store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}v_abs_v2i16:
|
2017-07-29 09:03:53 +08:00
|
|
|
; GFX9: global_load_dword [[VAL:v[0-9]+]]
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
|
|
|
|
|
; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
|
2019-06-20 07:37:43 +08:00
|
|
|
; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
|
2017-02-28 06:15:25 +08:00
|
|
|
|
2020-02-25 22:38:57 +08:00
|
|
|
; VI-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
|
|
|
|
; VI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16,
|
|
|
|
|
; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
|
|
|
|
|
; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
|
|
|
|
|
; VI-DAG: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
|
|
; VI-DAG: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
2017-02-28 06:15:25 +08:00
|
|
|
; VI: v_add_u16_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}
|
2017-06-04 01:39:47 +08:00
|
|
|
; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[TWO]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
2017-02-28 06:15:25 +08:00
|
|
|
; VI-NOT: v_and_b32
|
|
|
|
|
; VI: v_or_b32_e32
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
|
|
|
|
|
; CI: buffer_load_dword v
|
|
|
|
|
; CI: v_lshrrev_b32_e32
|
[DAGCombiner] Combine OR as ADD when no common bits are set
Summary:
The DAGCombiner is rewriting (canonicalizing) an ISD::ADD
with no common bits set in the operands as an ISD::OR node.
This could sometimes result in "missing out" on some
combines that normally are performed for ADD. To be more
specific this could happen if we already have rewritten an
ADD into OR, and later (after legalizations or combines)
we expose patterns that could have been optimized if we
had seen the OR as an ADD (e.g. reassociations based on ADD).
To make the DAG combiner less sensitive to if ADD or OR is
used for these "no common bits set" ADD/OR operations we
now apply most of the ADD combines also to an OR operation,
when value tracking indicates that the operands have no
common bits set.
Reviewers: spatel, RKSimon, craig.topper, kparzysz
Reviewed By: spatel
Subscribers: arsenm, rampitec, lebedev.ri, jvesely, nhaehnle, hiraditya, javed.absar, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59758
llvm-svn: 358965
2019-04-23 18:01:08 +08:00
|
|
|
; CI-DAG: v_sub_i32_e32
|
|
|
|
|
; CI-DAG: v_bfe_i32
|
|
|
|
|
; CI-DAG: v_bfe_i32
|
|
|
|
|
; CI-DAG: v_max_i32
|
|
|
|
|
; CI-DAG: v_max_i32
|
|
|
|
|
; CI-DAG: v_add_i32
|
|
|
|
|
; CI-DAG: v_add_i32
|
|
|
|
|
; CI-DAG: v_or_b32
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
|
%gep.in = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %src, i32 %tid
|
|
|
|
|
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
|
|
|
|
|
%val = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in, align 4
|
|
|
|
|
%neg = sub <2 x i16> zeroinitializer, %val
|
|
|
|
|
%cond = icmp sgt <2 x i16> %val, %neg
|
|
|
|
|
%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
|
|
|
|
|
%res2 = add <2 x i16> %res, <i16 2, i16 2>
|
|
|
|
|
store <2 x i16> %res2, <2 x i16> addrspace(1)* %gep.out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}s_abs_v2i16_2:
|
|
|
|
|
; GFX9: s_load_dword [[VAL:s[0-9]+]]
|
|
|
|
|
; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
|
|
|
|
|
; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
|
2019-06-20 07:37:43 +08:00
|
|
|
; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @s_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%z0 = insertelement <2 x i16> undef, i16 0, i16 0
|
|
|
|
|
%z1 = insertelement <2 x i16> %z0, i16 0, i16 1
|
|
|
|
|
%t0 = insertelement <2 x i16> undef, i16 2, i16 0
|
|
|
|
|
%t1 = insertelement <2 x i16> %t0, i16 2, i16 1
|
|
|
|
|
%neg = sub <2 x i16> %z1, %val
|
|
|
|
|
%cond = icmp sgt <2 x i16> %val, %neg
|
|
|
|
|
%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
|
|
|
|
|
%res2 = add <2 x i16> %res, %t1
|
|
|
|
|
store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}v_abs_v2i16_2:
|
2019-09-20 00:44:38 +08:00
|
|
|
; GFX9: global_load_dword [[VAL:v[0-9]+]]
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
|
|
|
|
|
; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
|
2019-06-20 07:37:43 +08:00
|
|
|
; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%z0 = insertelement <2 x i16> undef, i16 0, i16 0
|
|
|
|
|
%z1 = insertelement <2 x i16> %z0, i16 0, i16 1
|
|
|
|
|
%t0 = insertelement <2 x i16> undef, i16 2, i16 0
|
|
|
|
|
%t1 = insertelement <2 x i16> %t0, i16 2, i16 1
|
2019-09-20 00:44:38 +08:00
|
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
|
|
%gep.in = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %src, i32 %tid
|
|
|
|
|
%val = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in, align 4
|
2017-02-28 06:15:25 +08:00
|
|
|
%neg = sub <2 x i16> %z1, %val
|
|
|
|
|
%cond = icmp sgt <2 x i16> %val, %neg
|
|
|
|
|
%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
|
|
|
|
|
%res2 = add <2 x i16> %res, %t1
|
|
|
|
|
store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}s_abs_v4i16:
|
2018-06-15 23:15:46 +08:00
|
|
|
; GFX9: s_load_dwordx2 s{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}, s[0:1], 0x2c
|
|
|
|
|
; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, s[[VAL0]]
|
|
|
|
|
; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, s[[VAL1]]
|
|
|
|
|
; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], s[[VAL0]], [[SUB0]]
|
|
|
|
|
; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], s[[VAL1]], [[SUB1]]
|
2019-06-20 07:37:43 +08:00
|
|
|
; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0]
|
|
|
|
|
; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @s_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %val) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%z0 = insertelement <4 x i16> undef, i16 0, i16 0
|
|
|
|
|
%z1 = insertelement <4 x i16> %z0, i16 0, i16 1
|
|
|
|
|
%z2 = insertelement <4 x i16> %z1, i16 0, i16 2
|
|
|
|
|
%z3 = insertelement <4 x i16> %z2, i16 0, i16 3
|
|
|
|
|
%t0 = insertelement <4 x i16> undef, i16 2, i16 0
|
|
|
|
|
%t1 = insertelement <4 x i16> %t0, i16 2, i16 1
|
|
|
|
|
%t2 = insertelement <4 x i16> %t1, i16 2, i16 2
|
|
|
|
|
%t3 = insertelement <4 x i16> %t2, i16 2, i16 3
|
|
|
|
|
%neg = sub <4 x i16> %z3, %val
|
|
|
|
|
%cond = icmp sgt <4 x i16> %val, %neg
|
|
|
|
|
%res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg
|
|
|
|
|
%res2 = add <4 x i16> %res, %t3
|
|
|
|
|
store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}v_abs_v4i16:
|
2019-09-20 00:44:38 +08:00
|
|
|
; GFX9: global_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
|
2017-02-28 06:15:25 +08:00
|
|
|
|
|
|
|
|
; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, v[[VAL0]]
|
|
|
|
|
; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], v[[VAL0]], [[SUB0]]
|
2019-06-20 07:37:43 +08:00
|
|
|
; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0]
|
2017-02-28 06:15:25 +08:00
|
|
|
|
|
|
|
|
; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, v[[VAL1]]
|
|
|
|
|
; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], v[[VAL1]], [[SUB1]]
|
2019-06-20 07:37:43 +08:00
|
|
|
; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0]
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %src) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%z0 = insertelement <4 x i16> undef, i16 0, i16 0
|
|
|
|
|
%z1 = insertelement <4 x i16> %z0, i16 0, i16 1
|
|
|
|
|
%z2 = insertelement <4 x i16> %z1, i16 0, i16 2
|
|
|
|
|
%z3 = insertelement <4 x i16> %z2, i16 0, i16 3
|
|
|
|
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%t0 = insertelement <4 x i16> undef, i16 2, i16 0
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%t1 = insertelement <4 x i16> %t0, i16 2, i16 1
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%t2 = insertelement <4 x i16> %t1, i16 2, i16 2
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%t3 = insertelement <4 x i16> %t2, i16 2, i16 3
|
2019-09-20 00:44:38 +08:00
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %src, i32 %tid
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%val = load <4 x i16>, <4 x i16> addrspace(1)* %gep.in, align 4
|
2017-02-28 06:15:25 +08:00
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%neg = sub <4 x i16> %z3, %val
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%cond = icmp sgt <4 x i16> %val, %neg
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%res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg
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%res2 = add <4 x i16> %res, %t3
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store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
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|
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|
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|
|
|
|
|
; GCN-LABEL: {{^}}s_min_max_v2i16:
|
2018-05-23 04:42:00 +08:00
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|
|
; GFX9: v_pk_max_i16
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|
|
; GFX9: v_pk_min_i16
|
2017-03-22 05:39:51 +08:00
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|
|
define amdgpu_kernel void @s_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%cond0 = icmp sgt <2 x i16> %val0, %val1
|
|
|
|
|
%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
|
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|
|
|
%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
|
|
|
|
|
|
|
|
|
|
store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
|
|
|
|
|
store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}v_min_max_v2i16:
|
2018-05-23 04:42:00 +08:00
|
|
|
; GFX9: v_pk_max_i16
|
|
|
|
|
; GFX9: v_pk_min_i16
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
|
|
|
|
|
%val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1
|
|
|
|
|
|
|
|
|
|
%cond0 = icmp sgt <2 x i16> %val0, %val1
|
|
|
|
|
%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
|
|
|
|
|
%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
|
|
|
|
|
|
|
|
|
|
store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
|
|
|
|
|
store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2018-05-23 04:42:00 +08:00
|
|
|
; GCN-LABEL: {{^}}s_min_max_v4i16:
|
2020-01-14 06:54:17 +08:00
|
|
|
; GFX9-DAG: v_pk_max_i16
|
|
|
|
|
; GFX9-DAG: v_pk_min_i16
|
|
|
|
|
; GFX9-DAG: v_pk_max_i16
|
|
|
|
|
; GFX9-DAG: v_pk_min_i16
|
2018-05-23 04:42:00 +08:00
|
|
|
define amdgpu_kernel void @s_min_max_v4i16(<4 x i16> addrspace(1)* %out0, <4 x i16> addrspace(1)* %out1, <4 x i16> %val0, <4 x i16> %val1) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%cond0 = icmp sgt <4 x i16> %val0, %val1
|
|
|
|
|
%sel0 = select <4 x i1> %cond0, <4 x i16> %val0, <4 x i16> %val1
|
|
|
|
|
%sel1 = select <4 x i1> %cond0, <4 x i16> %val1, <4 x i16> %val0
|
|
|
|
|
|
|
|
|
|
store volatile <4 x i16> %sel0, <4 x i16> addrspace(1)* %out0, align 4
|
|
|
|
|
store volatile <4 x i16> %sel1, <4 x i16> addrspace(1)* %out1, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}v_min_max_v2i16_user:
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @v_min_max_v2i16_user(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 {
|
2017-02-28 06:15:25 +08:00
|
|
|
%val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
|
|
|
|
|
%val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1
|
|
|
|
|
|
|
|
|
|
%cond0 = icmp sgt <2 x i16> %val0, %val1
|
|
|
|
|
%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
|
|
|
|
|
%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
|
|
|
|
|
|
|
|
|
|
store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
|
|
|
|
|
store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
|
|
|
|
|
store volatile <2 x i1> %cond0, <2 x i1> addrspace(1)* undef
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}u_min_max_v2i16:
|
2017-05-31 00:49:24 +08:00
|
|
|
; GFX9: v_pk_max_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
2017-02-28 06:15:25 +08:00
|
|
|
; GFX9: v_pk_min_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
|
2017-03-22 05:39:51 +08:00
|
|
|
define amdgpu_kernel void @u_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) nounwind {
|
2017-02-28 06:15:25 +08:00
|
|
|
%cond0 = icmp ugt <2 x i16> %val0, %val1
|
|
|
|
|
%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
|
|
|
|
|
%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
|
|
|
|
|
|
|
|
|
|
store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
|
|
|
|
|
store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
|
|
|
|
|
|
|
attributes #0 = { nounwind }
|
|
|
|
|
attributes #1 = { nounwind readnone }
|