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[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
#
# This test gave "Use not jointly dominated by defs" when
# removePartialRedundancy attempted to prune and then re-extend a subrange.
#
# GCN: {{^body}}
---
name: _amdgpu_ps_main
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%21:vgpr_32 = nofpexcept V_TRUNC_F32_e32 undef %22:vgpr_32, implicit $mode, implicit $exec
%23:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %21, implicit $mode, implicit $exec
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
%108:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec
undef %109.sub1:vreg_128 = COPY %108
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
%28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sgpr_128, 3044, 0, 0 :: (dereferenceable invariant load 4)
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
S_CMP_EQ_U32 killed %28, 0, implicit-def $scc
S_CBRANCH_SCC0 %bb.2, implicit killed $scc
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.1:
%138:vreg_128 = COPY killed %109
S_BRANCH %bb.9
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.2:
successors: %bb.3, %bb.4
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
S_CBRANCH_SCC0 %bb.4, implicit undef $scc
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.3:
%136:vreg_128 = COPY killed %109
S_BRANCH %bb.5
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.4:
%136:vreg_128 = COPY killed %109
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.5:
successors: %bb.6, %bb.8
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
%110:vreg_128 = COPY killed %136
dead %32:sreg_32_xm0 = S_MOV_B32 0
%111:vreg_128 = COPY %110
%111.sub3:vreg_128 = COPY undef %32
S_CBRANCH_SCC1 %bb.8, implicit undef $scc
S_BRANCH %bb.6
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.6:
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
%36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sgpr_128, 2708, 0, 0 :: (dereferenceable invariant load 4)
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%39:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %110.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $mode, implicit $exec
%40:vgpr_32 = nofpexcept V_MAD_F32 0, %111.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $mode, implicit $exec
%41:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 0, 0, killed %40, 1, 0, implicit $mode, implicit $exec
%43:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %39, implicit $mode, implicit $exec
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
%44:vgpr_32 = COPY killed %43
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%44:vgpr_32 = nofpexcept V_MAC_F32_e32 0, killed %41, %44, implicit $mode, implicit $exec
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
%47:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
%46:vgpr_32 = COPY killed %47
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%46:vgpr_32 = nofpexcept V_MAC_F32_e32 0, killed %39, %46, implicit $mode, implicit $exec
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
undef %115.sub0:vreg_128 = COPY %46
%115.sub1:vreg_128 = COPY killed %46
%115.sub2:vreg_128 = COPY killed %44
%50:sreg_64_xexec = V_CMP_NE_U32_e64 0, killed %36, implicit $exec
dead %118:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%137:vreg_128 = IMPLICIT_DEF
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.7:
successors: %bb.7, %bb.8
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
%119:vreg_128 = COPY killed %137
%121:vreg_128 = COPY killed %119
%121.sub3:vreg_128 = COPY undef %32
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%56:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub2, %121.sub2, implicit $mode, implicit $exec
%59:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub1, %121.sub1, implicit $mode, implicit $exec
%62:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub0, killed %121.sub0, implicit $mode, implicit $exec
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
undef %117.sub0:vreg_128 = COPY killed %62
%117.sub1:vreg_128 = COPY killed %59
%117.sub2:vreg_128 = COPY killed %56
%64:sreg_64 = S_AND_B64 $exec, %50, implicit-def dead $scc
$vcc = COPY killed %64
%137:vreg_128 = COPY killed %117
S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
S_BRANCH %bb.8
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.8:
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sgpr_128, 2704, 0, 0 :: (dereferenceable invariant load 4)
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
%138:vreg_128 = COPY killed %111
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.9:
%113:vreg_128 = COPY killed %138
S_CBRANCH_SCC1 %bb.18, implicit undef $scc
S_BRANCH %bb.10
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.10:
S_CBRANCH_SCC1 %bb.12, implicit undef $scc
S_BRANCH %bb.11
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.11:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.12:
successors: %bb.13, %bb.18
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
S_CBRANCH_SCC1 %bb.18, implicit undef $scc
S_BRANCH %bb.13
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.13:
successors: %bb.14, %bb.17
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
S_CBRANCH_SCC1 %bb.17, implicit undef $scc
S_BRANCH %bb.14
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.14:
S_CBRANCH_SCC1 %bb.16, implicit undef $scc
S_BRANCH %bb.15
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.15:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.16:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.17:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.18:
S_CBRANCH_SCC1 %bb.26, implicit undef $scc
S_BRANCH %bb.19
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.19:
S_CBRANCH_SCC1 %bb.26, implicit undef $scc
S_BRANCH %bb.20
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.20:
S_CBRANCH_SCC1 %bb.25, implicit undef $scc
S_BRANCH %bb.21
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.21:
successors: %bb.22, %bb.24
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
S_CBRANCH_SCC1 %bb.24, implicit undef $scc
S_BRANCH %bb.22
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.22:
successors: %bb.23, %bb.24
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
S_CBRANCH_SCC1 %bb.24, implicit undef $scc
S_BRANCH %bb.23
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.23:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.24:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.25:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.26:
S_CBRANCH_SCC1 %bb.33, implicit undef $scc
S_BRANCH %bb.27
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.27:
S_CBRANCH_SCC1 %bb.33, implicit undef $scc
S_BRANCH %bb.28
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.28:
dead %77:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%78:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %113.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 1065353216, 0, 0, implicit $mode, implicit $exec
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
dead %80:sreg_32_xm0 = S_MOV_B32 0
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
dead %82:vgpr_32 = nofpexcept V_MUL_F32_e32 killed %78, %78, implicit $mode, implicit $exec
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
dead %126:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
dead %125:vreg_128 = IMPLICIT_DEF
dead %91:sreg_32_xm0 = S_MOV_B32 2143289344
%96:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc
%139:vreg_128 = IMPLICIT_DEF
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.29:
successors: %bb.30, %bb.31
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
dead %127:vreg_128 = COPY killed %139
S_CBRANCH_SCC0 %bb.31, implicit undef $scc
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.30:
S_BRANCH %bb.32
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.31:
successors: %bb.32, %bb.34
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
$vcc = COPY %96
S_CBRANCH_VCCNZ %bb.34, implicit killed $vcc
S_BRANCH %bb.32
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.32:
dead %130:vreg_128 = IMPLICIT_DEF
dead %128:vreg_128 = COPY undef %130
%139:vreg_128 = IMPLICIT_DEF
S_BRANCH %bb.29
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.33:
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
bb.34:
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0
[RegisterCoalescer] Fix for assert in removePartialRedundancy Summary: I got "Use not jointly dominated by defs" when removePartialRedundancy attempted to prune then re-extend a subrange whose only liveness was a dead def at the copy being removed. V2: Removed junk from test. Improved comment. V3: Addressed minor review comments. Subscribers: MatzeB, qcolombet, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D50914 Change-Id: I6f894e9f517f71e921e0c6d81d28c5f344db8dad llvm-svn: 340549
2018-08-24 01:28:33 +08:00
...