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llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.rel...

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AMDGPU: Have a few selection failure tests check both paths SelectionDAG and GlobalISel take different failure paths for these and end up producing different failure errors. Check both so the test passes when the default is switched.
2020-07-30 10:01:32 +08:00
; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-SDAG %s
; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s
AMDGPU: Add intrinsics for DS GWS semaphore instructions llvm-svn: 363983
2019-06-21 05:11:42 +08:00
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %s
AMDGPU: Have a few selection failure tests check both paths SelectionDAG and GlobalISel take different failure paths for these and end up producing different failure errors. Check both so the test passes when the default is switched.
2020-07-30 10:01:32 +08:00
; GFX6ERR-SDAG: LLVM ERROR: Cannot select: intrinsic %llvm.amdgcn.ds.gws.sema.release.all
; GFX6ERR-GISEL: LLVM ERROR: cannot select: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.release.all), %{{[0-9]+}}:sgpr(s32) :: (store 4 into custom "GWSResource") (in function: gws_sema_release_all_offset0)
AMDGPU: Add intrinsics for DS GWS semaphore instructions llvm-svn: 363983
2019-06-21 05:11:42 +08:00
; GCN-LABEL: {{^}}gws_sema_release_all_offset0:
AMDGPU: Don't rely on m0 being -1 for GWS offsets This only works if the high bits of m0 are also 0, so m0 would have to be set to 0xffff. llvm-svn: 366608
2019-07-20 04:01:24 +08:00
; NOLOOP-DAG: s_mov_b32 m0, 0{{$}}
; NOLOOP: ds_gws_sema_release_all gds{{$}}
AMDGPU: Add intrinsics for DS GWS semaphore instructions llvm-svn: 363983
2019-06-21 05:11:42 +08:00
AMDGPU: Don't rely on m0 being -1 for GWS offsets This only works if the high bits of m0 are also 0, so m0 would have to be set to 0xffff. llvm-svn: 366608
2019-07-20 04:01:24 +08:00
; LOOP: s_mov_b32 m0, 0{{$}}
AMDGPU: Add intrinsics for DS GWS semaphore instructions llvm-svn: 363983
2019-06-21 05:11:42 +08:00
; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]:
; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
AMDGPU: Don't rely on m0 being -1 for GWS offsets This only works if the high bits of m0 are also 0, so m0 would have to be set to 0xffff. llvm-svn: 366608
2019-07-20 04:01:24 +08:00
; LOOP-NEXT: ds_gws_sema_release_all gds
AMDGPU: Add intrinsics for DS GWS semaphore instructions llvm-svn: 363983
2019-06-21 05:11:42 +08:00
; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
define amdgpu_kernel void @gws_sema_release_all_offset0(i32 %val) #0 {
call void @llvm.amdgcn.ds.gws.sema.release.all(i32 0)
ret void
}
declare void @llvm.amdgcn.ds.gws.sema.release.all(i32) #0
attributes #0 = { convergent inaccessiblememonly nounwind }