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Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx803 -run-pass=simple-register-coalescing -o - %s | FileCheck -check-prefix=GCN %s
# With one version of the D48102 fix, this test failed with
# Assertion failed: (Id != S.end() && T != S.end() && T->valno == Id->valno), function pruneSubRegValues, file ../lib/CodeGen/RegisterCoalescer.cpp, line 2870.
# GCN: {{^body}}
--- |
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
target triple = "amdgcn--amdpal"
; Function Attrs: nounwind
define amdgpu_cs void @_amdgpu_cs_main(<3 x i32> %arg) #0 {
ret void
}
attributes #0 = { nounwind "target-cpu"="gfx803" }
...
---
name: _amdgpu_cs_main
tracksRegLiveness: true
liveins:
- { reg: '$vgpr0', virtual-reg: '%0' }
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.21(0x40000000)
liveins: $vgpr0, $vgpr1, $vgpr2
%0:vgpr_32 = COPY killed $vgpr0
S_CBRANCH_SCC1 %bb.21, implicit undef $scc
bb.1:
successors: %bb.2(0x40000000), %bb.17(0x40000000)
S_CBRANCH_SCC1 %bb.17, implicit undef $scc
bb.2:
successors: %bb.4(0x40000000), %bb.3(0x40000000)
%1:sreg_32_xm0 = S_MOV_B32 0
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
undef %3.sub0:vreg_128 = COPY killed %0
%3.sub2:vreg_128 = COPY killed %2
[AMDGPU] Use SGPR instead of SReg classes 12994a70cf7 did this for 128-bit classes: SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. This patch extends it to all classes > 64 bits, for consistency. Differential Revision: https://reviews.llvm.org/D78622
2020-04-22 18:08:08 +08:00
undef %4.sub0:sgpr_256 = COPY %1
%4.sub1:sgpr_256 = COPY %1
%4.sub2:sgpr_256 = COPY %1
%4.sub3:sgpr_256 = COPY %1
%4.sub4:sgpr_256 = COPY %1
%4.sub5:sgpr_256 = COPY %1
%4.sub6:sgpr_256 = COPY %1
%4.sub7:sgpr_256 = COPY killed %1
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
%5:vgpr_32 = IMAGE_LOAD_V1_V4 killed %3, killed %4, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%6:vgpr_32 = nofpexcept V_MAD_F32 0, killed %5, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
%7:vgpr_32 = nofpexcept V_RCP_F32_e32 killed %6, implicit $mode, implicit $exec
%8:vgpr_32 = nofpexcept V_MUL_F32_e32 0, killed %7, implicit $mode, implicit $exec
%9:vgpr_32 = nofpexcept V_MAD_F32 0, killed %8, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
dead %10:vgpr_32 = nofpexcept V_MAC_F32_e32 undef %11:vgpr_32, undef %12:vgpr_32, undef %10, implicit $mode, implicit $exec
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
undef %13.sub0:vreg_128 = COPY %9
%14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
S_CBRANCH_SCC0 %bb.4, implicit undef $scc
bb.3:
successors: %bb.6(0x80000000)
%15:vreg_128 = IMPLICIT_DEF
AMDGPU: Make VReg_1 size be 1 This was getting chosen as the preferred 32-bit register class based on how TableGen selects subregister classes. llvm-svn: 371438
2019-09-10 02:43:29 +08:00
%16:vgpr_32 = COPY killed %14
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
S_BRANCH %bb.6
bb.4:
successors: %bb.5(0x40000000), %bb.7(0x40000000)
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%17:vgpr_32 = nofpexcept V_MAD_F32 0, killed %9, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
%18:vgpr_32 = nofpexcept V_MIN_F32_e32 1065353216, killed %17, implicit $mode, implicit $exec
%19:sreg_64_xexec = nofpexcept V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %18, 0, implicit $mode, implicit $exec
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
%20:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
[AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers This commit allows v_cndmask_b32_e64 with abs, neg source modifiers on src0, src1 to be assembled and disassembled. This does appear to be allowed, even though they are floating point modifiers and the operand type is b32. To do this, I added src0_modifiers and src1_modifiers to the MachineInstr, which involved fixing up several places in codegen and mir tests. Differential Revision: https://reviews.llvm.org/D59191 Change-Id: I69bf4a8c73ebc65744f6110bb8fc4e937d79fbea llvm-svn: 356398
2019-03-19 03:25:39 +08:00
%21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, killed %20, killed %19, implicit $exec
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%22:sreg_64 = nofpexcept V_CMP_LT_F32_e64 0, 0, 0, killed %21, 0, implicit $mode, implicit $exec
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
%23:sreg_64 = COPY $exec, implicit-def $exec
%24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc
$exec = S_MOV_B64_term killed %24
SI_MASK_BRANCH %bb.7, implicit $exec
S_BRANCH %bb.5
bb.5:
successors: %bb.7(0x80000000)
S_BRANCH %bb.7
bb.6:
successors: %bb.8(0x40000000), %bb.10(0x40000000)
AMDGPU: Make VReg_1 size be 1 This was getting chosen as the preferred 32-bit register class based on how TableGen selects subregister classes. llvm-svn: 371438
2019-09-10 02:43:29 +08:00
%25:vgpr_32 = COPY killed %16
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
%26:vreg_128 = COPY killed %15
%27:sreg_64 = V_CMP_NE_U32_e64 0, killed %25, implicit $exec
%28:sreg_64 = S_AND_B64 $exec, killed %27, implicit-def dead $scc
$vcc = COPY killed %28
%29:vreg_128 = COPY killed %26
S_CBRANCH_VCCNZ %bb.8, implicit killed $vcc
S_BRANCH %bb.10
bb.7:
successors: %bb.6(0x80000000)
$exec = S_OR_B64 $exec, killed %23, implicit-def $scc
%30:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%15:vreg_128 = COPY %13
AMDGPU: Make VReg_1 size be 1 This was getting chosen as the preferred 32-bit register class based on how TableGen selects subregister classes. llvm-svn: 371438
2019-09-10 02:43:29 +08:00
%16:vgpr_32 = COPY killed %30
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
S_BRANCH %bb.6
bb.8:
successors: %bb.9(0x40000000), %bb.11(0x40000000)
%31:vreg_128 = COPY killed %13
S_CBRANCH_SCC1 %bb.11, implicit undef $scc
S_BRANCH %bb.9
bb.9:
successors: %bb.11(0x80000000)
%32:sreg_32_xm0 = S_MOV_B32 0
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
undef %33.sub0:sgpr_128 = COPY %32
%33.sub1:sgpr_128 = COPY %32
%33.sub2:sgpr_128 = COPY %32
%33.sub3:sgpr_128 = COPY killed %32
%34:sgpr_128 = COPY killed %33
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
%35:vreg_128 = COPY killed %34
%31:vreg_128 = COPY killed %35
S_BRANCH %bb.11
bb.10:
successors: %bb.14(0x80000000)
%36:vreg_128 = COPY killed %29
S_BRANCH %bb.14
bb.11:
successors: %bb.13(0x40000000), %bb.12(0x40000000)
%37:vreg_128 = COPY killed %31
S_CBRANCH_SCC0 %bb.13, implicit undef $scc
bb.12:
successors: %bb.10(0x80000000)
%29:vreg_128 = COPY killed %37
S_BRANCH %bb.10
bb.13:
successors: %bb.10(0x80000000)
%29:vreg_128 = COPY killed %37
S_BRANCH %bb.10
bb.14:
successors: %bb.15(0x40000000), %bb.16(0x40000000)
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%38:vgpr_32 = nofpexcept V_MAD_F32 0, killed %36.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $mode, implicit $exec
%39:vgpr_32 = nofpexcept V_MAD_F32 0, killed %38, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
%40:vgpr_32 = nofpexcept V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $mode, implicit $exec
%41:vgpr_32 = nofpexcept V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $mode, implicit $exec
%42:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 killed %41, implicit $mode, implicit $exec
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
%43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sgpr_128, 12, 0, 0 :: (dereferenceable invariant load 4)
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
%45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec
%46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
2019-10-10 15:11:33 +08:00
%47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
%49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec
%50:sreg_64 = COPY $exec, implicit-def $exec
%51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
$exec = S_MOV_B64_term killed %51
SI_MASK_BRANCH %bb.16, implicit $exec
S_BRANCH %bb.15
bb.15:
successors: %bb.16(0x80000000)
bb.16:
successors: %bb.17(0x80000000)
$exec = S_OR_B64 $exec, killed %50, implicit-def $scc
S_BRANCH %bb.17
bb.17:
successors: %bb.21(0x40000000), %bb.18(0x40000000)
S_CBRANCH_SCC1 %bb.21, implicit undef $scc
bb.18:
successors: %bb.19(0x40000000), %bb.20(0x40000000)
S_CBRANCH_SCC1 %bb.19, implicit undef $scc
S_BRANCH %bb.20
bb.19:
successors: %bb.20(0x80000000)
bb.20:
successors: %bb.21(0x80000000)
bb.21:
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0
Improve handling of COPY instructions with identical value numbers Testcases provided by Tim Renouf. Differential Revision: https://reviews.llvm.org/D48102 llvm-svn: 335472
2018-06-25 21:46:41 +08:00
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