forked from OSchip/llvm-project
102 lines
2.9 KiB
LLVM
102 lines
2.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1030 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1010 %s
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; For gfx1010, overestimate the branch size in case we need to insert
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; a nop for the buggy offset.
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; GCN-LABEL: long_forward_scc_branch_3f_offset_bug:
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; GFX1030: s_cmp_lg_u32
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; GFX1030-NEXT: s_cbranch_scc1 [[ENDBB:BB[0-9]+_[0-9]+]]
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; GFX1010: s_cmp_lg_u32
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; GFX1010-NEXT: s_cbranch_scc0 [[RELAX_BB:BB[0-9]+_[0-9]+]]
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; GFX1010: s_getpc_b64
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; GFX1010-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[ENDBB:BB[0-9]+_[0-9]+]]-(BB
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; GFX1010-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}
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; GFX1010: [[RELAX_BB]]:
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; GCN: v_nop
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; GCN: s_sleep
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; GCN: s_cbranch_scc1
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; GCN: [[ENDBB]]:
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; GCN: global_store_dword
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define amdgpu_kernel void @long_forward_scc_branch_3f_offset_bug(i32 addrspace(1)* %arg, i32 %cnd0) #0 {
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bb0:
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%cmp0 = icmp eq i32 %cnd0, 0
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br i1 %cmp0, label %bb2, label %bb3
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bb2:
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%val = call i32 asm sideeffect
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"s_mov_b32 $0, 0
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "=s"() ; 20 * 12 = 240
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call void @llvm.amdgcn.s.sleep(i32 0) ; +4 = 244
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%cmp1 = icmp eq i32 %val, 0 ; +4 = 248
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br i1 %cmp1, label %bb2, label %bb3 ; +4 (gfx1030), +8 with workaround (gfx1010)
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bb3:
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store volatile i32 %cnd0, i32 addrspace(1)* %arg
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ret void
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}
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; GCN-LABEL: {{^}}long_forward_exec_branch_3f_offset_bug:
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; GFX1030: v_cmp_eq_u32
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; GFX1030: s_and_saveexec_b32
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; GFX1030-NEXT: s_cbranch_execnz [[RELAX_BB:BB[0-9]+_[0-9]+]]
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; GFX1010: v_cmp_eq_u32
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; GFX1010: s_and_saveexec_b32
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; GFX1010-NEXT: s_cbranch_execnz [[RELAX_BB:BB[0-9]+_[0-9]+]]
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; GCN: s_getpc_b64
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; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[ENDBB:BB[0-9]+_[0-9]+]]-(BB
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; GCN-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: [[RELAX_BB]]:
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; GCN: v_nop
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; GCN: s_sleep
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; GCN: s_cbranch_execz
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; GCN: [[ENDBB]]:
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; GCN: global_store_dword
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define void @long_forward_exec_branch_3f_offset_bug(i32 addrspace(1)* %arg, i32 %cnd0) #0 {
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bb0:
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%cmp0 = icmp eq i32 %cnd0, 0
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br i1 %cmp0, label %bb2, label %bb3
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bb2:
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%val = call i32 asm sideeffect
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"v_mov_b32 $0, 0
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "=v"() ; 20 * 12 = 240
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call void @llvm.amdgcn.s.sleep(i32 0) ; +4 = 244
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%cmp1 = icmp eq i32 %val, 0 ; +4 = 248
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br i1 %cmp1, label %bb2, label %bb3 ; +4 (gfx1030), +8 with workaround (gfx1010)
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bb3:
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store volatile i32 %cnd0, i32 addrspace(1)* %arg
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ret void
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}
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declare void @llvm.amdgcn.s.sleep(i32 immarg)
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