maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

1732 lines
108 KiB
LLVM
Raw Normal View History

AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -O0 -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck -check-prefix=HSA-VI %s
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=fiji -O0 -amdgpu-ir-lower-kernel-arguments=0 -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck -check-prefix=LEGACY-MESA-VI %s
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
; HSA-VI-LABEL: name: i8_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8)
; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i8_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = zext i8 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
; HSA-VI-LABEL: name: i8_zext_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8)
; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i8_zext_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = zext i8 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
; HSA-VI-LABEL: name: i8_sext_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8)
; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i8_sext_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s8)
; LEGACY-MESA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = sext i8 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
; HSA-VI-LABEL: name: i16_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i16_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 4, addrspace 4)
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = zext i16 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
; HSA-VI-LABEL: name: i16_zext_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i16_zext_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 4, addrspace 4)
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = zext i16 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
; HSA-VI-LABEL: name: i16_sext_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s16)
; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i16_sext_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 4, addrspace 4)
; LEGACY-MESA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s16)
; LEGACY-MESA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = sext i16 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind {
; HSA-VI-LABEL: name: i32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store i32 %in, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind {
; HSA-VI-LABEL: name: f32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: f32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store float %in, float addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) {
; HSA-VI-LABEL: name: v2i8_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<2 x s8>), [[LOAD]](p1) :: (store 2 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v2i8_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 2, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<2 x s8>), [[LOAD]](p1) :: (store 2 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <2 x i8> %in, <2 x i8> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) {
; HSA-VI-LABEL: name: v2i16_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<2 x s16>), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v2i16_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<2 x s16>), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <2 x i16> %in, <2 x i16> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind {
; HSA-VI-LABEL: name: v2i32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<2 x s32>), [[LOAD]](p1) :: (store 8 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v2i32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<2 x s32>), [[LOAD]](p1) :: (store 8 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind {
; HSA-VI-LABEL: name: v2f32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<2 x s32>), [[LOAD]](p1) :: (store 8 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v2f32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<2 x s32>), [[LOAD]](p1) :: (store 8 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind {
; HSA-VI-LABEL: name: v3i8_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 3, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<3 x s8>), [[LOAD]](p1) :: (store 3 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v3i8_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 3, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<3 x s8>), [[LOAD]](p1) :: (store 3 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind {
; HSA-VI-LABEL: name: v3i16_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 6, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<3 x s16>), [[LOAD]](p1) :: (store 6 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v3i16_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 6, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<3 x s16>), [[LOAD]](p1) :: (store 6 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind {
; HSA-VI-LABEL: name: v3i32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 12, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<3 x s32>), [[LOAD]](p1) :: (store 12 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v3i32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 12, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<3 x s32>), [[LOAD]](p1) :: (store 12 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind {
; HSA-VI-LABEL: name: v3f32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 12, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<3 x s32>), [[LOAD]](p1) :: (store 12 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v3f32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 12, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<3 x s32>), [[LOAD]](p1) :: (store 12 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) {
; HSA-VI-LABEL: name: v4i8_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<4 x s8>), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v4i8_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<4 x s8>), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <4 x i8> %in, <4 x i8> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) {
; HSA-VI-LABEL: name: v4i16_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<4 x s16>), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v4i16_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<4 x s16>), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <4 x i16> %in, <4 x i16> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind {
; HSA-VI-LABEL: name: v4i32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<4 x s32>), [[LOAD]](p1) :: (store 16 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v4i32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<4 x s32>), [[LOAD]](p1) :: (store 16 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
; HSA-VI-LABEL: name: v4f32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<4 x s32>), [[LOAD]](p1) :: (store 16 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v4f32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<4 x s32>), [[LOAD]](p1) :: (store 16 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) {
; HSA-VI-LABEL: name: v8i8_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<8 x s8>), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v8i8_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<8 x s8>), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <8 x i8> %in, <8 x i8> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) {
; HSA-VI-LABEL: name: v8i16_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<8 x s16>), [[LOAD]](p1) :: (store 16 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v8i16_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<8 x s16>), [[LOAD]](p1) :: (store 16 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <8 x i16> %in, <8 x i16> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind {
; HSA-VI-LABEL: name: v8i32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 32, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<8 x s32>), [[LOAD]](p1) :: (store 32 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v8i32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 32, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<8 x s32>), [[LOAD]](p1) :: (store 32 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind {
; HSA-VI-LABEL: name: v8f32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 32, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<8 x s32>), [[LOAD]](p1) :: (store 32 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v8f32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 32, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<8 x s32>), [[LOAD]](p1) :: (store 32 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) {
; HSA-VI-LABEL: name: v16i8_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<16 x s8>), [[LOAD]](p1) :: (store 16 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v16i8_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<16 x s8>), [[LOAD]](p1) :: (store 16 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <16 x i8> %in, <16 x i8> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) {
; HSA-VI-LABEL: name: v16i16_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 32, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<16 x s16>), [[LOAD]](p1) :: (store 32 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v16i16_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s16>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 32, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<16 x s16>), [[LOAD]](p1) :: (store 32 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <16 x i16> %in, <16 x i16> addrspace(1)* %out
ret void
}
define amdgpu_kernel void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind {
; HSA-VI-LABEL: name: v16i32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 64, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<16 x s32>), [[LOAD]](p1) :: (store 64 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v16i32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 64, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<16 x s32>), [[LOAD]](p1) :: (store 64 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind {
; HSA-VI-LABEL: name: v16f32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 64, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](<16 x s32>), [[LOAD]](p1) :: (store 64 into %ir.out, align 4, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: v16f32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 64, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](<16 x s32>), [[LOAD]](p1) :: (store 64 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @kernel_arg_i64(i64 addrspace(1)* %out, i64 %a) nounwind {
; HSA-VI-LABEL: name: kernel_arg_i64
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: kernel_arg_i64
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
store i64 %a, i64 addrspace(1)* %out, align 8
ret void
}
define amdgpu_kernel void @f64_kernel_arg(double addrspace(1)* %out, double %in) {
; HSA-VI-LABEL: name: f64_kernel_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: f64_kernel_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
entry:
store double %in, double addrspace(1)* %out
ret void
}
define amdgpu_kernel void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind {
; HSA-VI-LABEL: name: i1_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: G_STORE [[LOAD1]](s1), [[LOAD]](p1) :: (store 1 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i1_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s1), [[LOAD]](p1) :: (store 1 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
store i1 %x, i1 addrspace(1)* %out, align 1
ret void
}
define amdgpu_kernel void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind {
; HSA-VI-LABEL: name: i1_arg_zext_i32
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s1)
; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i1_arg_zext_i32
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s1)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = zext i1 %x to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind {
; HSA-VI-LABEL: name: i1_arg_zext_i64
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD1]](s1)
; HSA-VI: G_STORE [[ZEXT]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i1_arg_zext_i64
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD1]](s1)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = zext i1 %x to i64
store i64 %ext, i64 addrspace(1)* %out, align 8
ret void
}
define amdgpu_kernel void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind {
; HSA-VI-LABEL: name: i1_arg_sext_i32
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s1)
; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i1_arg_sext_i32
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD1]](s1)
; LEGACY-MESA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = sext i1 %x to i32
store i32 %ext, i32addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind {
; HSA-VI-LABEL: name: i1_arg_sext_i64
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD1]](s1)
; HSA-VI: G_STORE [[SEXT]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: i1_arg_sext_i64
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
; LEGACY-MESA-VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD1]](s1)
; LEGACY-MESA-VI: G_STORE [[SEXT]](s64), [[LOAD]](p1) :: (store 8 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
%ext = sext i1 %x to i64
store i64 %ext, i64 addrspace(1)* %out, align 8
ret void
}
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; 0-sized arguments do not add a slot to the argument register set, so
; waste an index in the virtual register array.
define amdgpu_kernel void @empty_struct_arg({} %arg0, i32 %arg1) nounwind {
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI-LABEL: name: empty_struct_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4, align 16, addrspace 4)
; HSA-VI: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: empty_struct_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4, addrspace 4)
; LEGACY-MESA-VI: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
store i32 %arg1, i32 addrspace(1)* undef
ret void
}
define amdgpu_kernel void @empty_array_arg([0 x i8] %arg0, i32 %arg1) nounwind {
; HSA-VI-LABEL: name: empty_array_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4, align 16, addrspace 4)
; HSA-VI: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; HSA-VI: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: empty_array_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 4, addrspace 4)
; LEGACY-MESA-VI: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; LEGACY-MESA-VI: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
store i32 %arg1, i32 addrspace(1)* undef
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
ret void
}
; The correct load offsets for these:
; load 4 from 0,
; load 8 from 8
; load 4 from 24
; load 8 from 32
; With the SelectionDAG argument lowering, the alignments for the
; struct members is not properly considered, making these wrong.
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8 %pad, {i32, i64} %arg1) {
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI-LABEL: name: struct_argument_alignment
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; HSA-VI: bb.1 (%ir-block.0):
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 16, addrspace 4)
[GlobalISel] Accept multiple vregs in lowerFormalArgs Change the interface of CallLowering::lowerFormalArguments to accept several virtual registers for each formal argument, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660. lowerCall will be refactored in the same way in follow-up patches. With this change, we forward the virtual registers generated for aggregates to CallLowering. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. We also copy the pack/unpackRegs helpers to CallLowering to facilitate this. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. AArch64 seems to have had a bug when lowering e.g. [1 x i8*], which was put into a s64 instead of a p0. Added a test-case which illustrates the problem more clearly (it crashes without this patch) and fixed the existing test-case to expect p0. AMDGPU has been updated to unpack into the virtual registers for kernels. I think the other code paths fall back for aggregates, so this should be NFC. Mips doesn't support aggregates yet, so it's also NFC. x86 seems to have code for dealing with aggregates, but I couldn't find the tests for it, so I just added a fallback to DAGISel if we get more than one virtual register for an argument. Differential Revision: https://reviews.llvm.org/D63549 llvm-svn: 364510
2019-06-27 16:54:17 +08:00
; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s128), 0
; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s128), 64
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 16, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; HSA-VI: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 16, align 8, addrspace 4)
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
; HSA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD2]](s128), 0
; HSA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD2]](s128), 64
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
; HSA-VI: [[C3:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; HSA-VI: [[COPY1:%[0-9]+]]:_(p1) = COPY [[C3]](p1)
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; HSA-VI: [[COPY2:%[0-9]+]]:_(p1) = COPY [[C3]](p1)
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
; HSA-VI: G_STORE [[EXTRACT]](s32), [[C3]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
; HSA-VI: G_STORE [[EXTRACT1]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; HSA-VI: G_STORE [[LOAD1]](s8), [[COPY2]](p1) :: (volatile store 1 into `i8 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
; HSA-VI: G_STORE [[EXTRACT2]](s32), [[C3]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
; HSA-VI: G_STORE [[EXTRACT3]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Fix MMO flags for kernel argument loads The DAG lowering sets dereferencable and invariant, not nontemporal. llvm-svn: 366597
2019-07-20 01:52:56 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: struct_argument_alignment
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
; LEGACY-MESA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s128), 0
; LEGACY-MESA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s128), 64
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 1, align 4, addrspace 4)
AMDGPU/GlobalISel: Fix legacy clover kernel argument ABI This had an extra attempt to align the pointer, which only did anything with a base kernel argument offset which only clover used to use.
2020-06-26 21:02:46 +08:00
; LEGACY-MESA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 60
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; LEGACY-MESA-VI: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 16, align 4, addrspace 4)
; LEGACY-MESA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD2]](s128), 0
; LEGACY-MESA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD2]](s128), 64
; LEGACY-MESA-VI: [[C3:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; LEGACY-MESA-VI: [[COPY1:%[0-9]+]]:_(p1) = COPY [[C3]](p1)
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; LEGACY-MESA-VI: [[COPY2:%[0-9]+]]:_(p1) = COPY [[C3]](p1)
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: G_STORE [[EXTRACT]](s32), [[C3]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[EXTRACT1]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s8), [[COPY2]](p1) :: (volatile store 1 into `i8 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: G_STORE [[EXTRACT2]](s32), [[C3]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[EXTRACT3]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
%val0 = extractvalue {i32, i64} %arg0, 0
%val1 = extractvalue {i32, i64} %arg0, 1
%val2 = extractvalue {i32, i64} %arg1, 0
%val3 = extractvalue {i32, i64} %arg1, 1
store volatile i32 %val0, i32 addrspace(1)* null
store volatile i64 %val1, i64 addrspace(1)* null
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
store volatile i8 %pad, i8 addrspace(1)* null
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
store volatile i32 %val2, i32 addrspace(1)* null
store volatile i64 %val3, i64 addrspace(1)* null
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
ret void
}
; No padding between i8 and next struct, but round up at end to 4 byte
; multiple.
define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) {
; HSA-VI-LABEL: name: packed_struct_argument_alignment
; HSA-VI: bb.1 (%ir-block.1):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(s96) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 12, align 16, addrspace 4)
[GlobalISel] Accept multiple vregs in lowerFormalArgs Change the interface of CallLowering::lowerFormalArguments to accept several virtual registers for each formal argument, instead of just one. This is a follow-up to D46018. CallLowering::lowerReturn was similarly refactored in D49660. lowerCall will be refactored in the same way in follow-up patches. With this change, we forward the virtual registers generated for aggregates to CallLowering. Therefore, the target can decide itself whether it wants to handle them as separate pieces or use one big register. We also copy the pack/unpackRegs helpers to CallLowering to facilitate this. ARM and AArch64 have been updated to use the passed in virtual registers directly, which means we no longer need to generate so many merge/extract instructions. AArch64 seems to have had a bug when lowering e.g. [1 x i8*], which was put into a s64 instead of a p0. Added a test-case which illustrates the problem more clearly (it crashes without this patch) and fixed the existing test-case to expect p0. AMDGPU has been updated to unpack into the virtual registers for kernels. I think the other code paths fall back for aggregates, so this should be NFC. Mips doesn't support aggregates yet, so it's also NFC. x86 seems to have code for dealing with aggregates, but I couldn't find the tests for it, so I just added a fallback to DAGISel if we get more than one virtual register for an argument. Differential Revision: https://reviews.llvm.org/D63549 llvm-svn: 364510
2019-06-27 16:54:17 +08:00
; HSA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s96), 0
; HSA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s96), 32
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 13
AMDGPU/GlobalISel: Regenerate checks Avoids extra diffs from the rename of G_GEP to G_PTR_ADD in the generated check variables in a future patch.
2020-05-08 22:29:25 +08:00
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s96) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 12, align 1, addrspace 4)
; HSA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD1]](s96), 0
; HSA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD1]](s96), 32
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; HSA-VI: [[C2:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; HSA-VI: [[COPY1:%[0-9]+]]:_(p1) = COPY [[C2]](p1)
; HSA-VI: G_STORE [[EXTRACT]](s32), [[C2]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
; HSA-VI: G_STORE [[EXTRACT1]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; HSA-VI: G_STORE [[EXTRACT2]](s32), [[C2]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
; HSA-VI: G_STORE [[EXTRACT3]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
; HSA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI-LABEL: name: packed_struct_argument_alignment
; LEGACY-MESA-VI: bb.1 (%ir-block.1):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(s96) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 12, align 4, addrspace 4)
; LEGACY-MESA-VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD]](s96), 0
; LEGACY-MESA-VI: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD]](s96), 32
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s96) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load 12, align 1, addrspace 4)
; LEGACY-MESA-VI: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD1]](s96), 0
; LEGACY-MESA-VI: [[EXTRACT3:%[0-9]+]]:_(s64) = G_EXTRACT [[LOAD1]](s96), 32
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
; LEGACY-MESA-VI: [[C2:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
; LEGACY-MESA-VI: [[COPY1:%[0-9]+]]:_(p1) = COPY [[C2]](p1)
; LEGACY-MESA-VI: G_STORE [[EXTRACT]](s32), [[C2]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: G_STORE [[EXTRACT1]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Fix skipping unused kernel arguments The tests in a5b9ad7e9aca1329ba310e638dafa58c47468a58 actually failed the verifier, which for some reason is not the default. Also add tests for 0-sized function arguments, which do not add entries to the expected register lists.
2020-07-08 01:57:09 +08:00
; LEGACY-MESA-VI: G_STORE [[EXTRACT2]](s32), [[C2]](p1) :: (volatile store 4 into `i32 addrspace(1)* null`, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[EXTRACT3]](s64), [[COPY1]](p1) :: (volatile store 8 into `i64 addrspace(1)* null`, addrspace 1)
AMDGPU/GlobalISel: Add baseline checks for legacy clover kernel ABI I'm not sure we actually need to support this now, since I think clover always explicitly uses amdgcn-mesa-mesa3d now, not the ill-defined amdgcn-- behavior.
2020-06-26 21:22:03 +08:00
; LEGACY-MESA-VI: S_ENDPGM 0
AMDGPU/GlobalISel: Uncomment some fixed tests
2020-06-26 21:30:10 +08:00
%val0 = extractvalue <{i32, i64}> %arg0, 0
%val1 = extractvalue <{i32, i64}> %arg0, 1
%val2 = extractvalue <{i32, i64}> %arg1, 0
%val3 = extractvalue <{i32, i64}> %arg1, 1
store volatile i32 %val0, i32 addrspace(1)* null
store volatile i64 %val1, i64 addrspace(1)* null
store volatile i32 %val2, i32 addrspace(1)* null
store volatile i64 %val3, i64 addrspace(1)* null
AMDGPU/GlobalISel: Implement custom kernel arg lowering Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
2018-07-06 01:01:20 +08:00
ret void
}
AMDGPU/GlobalISel: Don't emit code for unused kernel arguments
2020-07-06 04:35:01 +08:00
define amdgpu_kernel void @unused_i32_arg(i32 addrspace(1)* nocapture %out, i32 %unused, i32 %in) nounwind {
; HSA-VI-LABEL: name: unused_i32_arg
; HSA-VI: bb.1.entry:
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: unused_i32_arg
; LEGACY-MESA-VI: bb.1.entry:
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: S_ENDPGM 0
entry:
ret void
}
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; Byref pointers should only be treated as offsets from kernarg
define amdgpu_kernel void @byref_constant_i8_arg(i32 addrspace(1)* nocapture %out, i8 addrspace(4)* byref(i8) %in.byref) {
; HSA-VI-LABEL: name: byref_constant_i8_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 1 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8)
; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_constant_i8_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 1 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s8)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i8, i8 addrspace(4)* %in.byref
%ext = zext i8 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_constant_i16_arg(i32 addrspace(1)* nocapture %out, i16 addrspace(4)* byref(i16) align 2 %in.byref) {
; HSA-VI-LABEL: name: byref_constant_i16_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 2 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_constant_i16_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 2 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
; LEGACY-MESA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i16, i16 addrspace(4)* %in.byref
%ext = zext i16 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) align 4 %in.byref, i32 %after.offset) {
; HSA-VI-LABEL: name: byref_constant_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; HSA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 4 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD2]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_constant_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; LEGACY-MESA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, align 16, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 4 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD2]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32 addrspace(4)* %in.byref
store volatile i32 %in, i32 addrspace(1)* %out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_constant_v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> addrspace(4)* byref(<4 x i32>) align(16) %in.byref, i32 %after.offset) {
; HSA-VI-LABEL: name: byref_constant_v4i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; HSA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, align 16, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD2:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 16 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD2]](<4 x s32>), [[LOAD]](p1) :: (volatile store 16 into %ir.out, align 4, addrspace 1)
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out.cast, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_constant_v4i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 68
; LEGACY-MESA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD2:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 16 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD2]](<4 x s32>), [[LOAD]](p1) :: (volatile store 16 into %ir.out, align 4, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out.cast, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load <4 x i32>, <4 x i32> addrspace(4)* %in.byref
store volatile <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
%out.cast = bitcast <4 x i32> addrspace(1)* %out to i32 addrspace(1)*
store volatile i32 %after.offset, i32 addrspace(1)* %out.cast, align 4
ret void
}
define amdgpu_kernel void @byref_align_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) align(256) %in.byref, i32 %after.offset) {
; HSA-VI-LABEL: name: byref_align_constant_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 256
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 260
; HSA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 4 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD2]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_align_constant_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 292
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 296
; LEGACY-MESA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, align 8, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 4 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD2]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32 addrspace(4)* %in.byref
store volatile i32 %in, i32 addrspace(1)* %out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(i32 addrspace(1)* nocapture %out, i8, <16 x i32> addrspace(4)* byref(<16 x i32>) align(64) %in.byref, i32 %after.offset) {
; HSA-VI-LABEL: name: byref_natural_align_constant_v16i32_arg
; HSA-VI: bb.1 (%ir-block.1):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 128
; HSA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, align 16, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD2:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 64 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD2]](<16 x s32>), [[LOAD]](p1) :: (volatile store 64 into %ir.cast.out, align 4, addrspace 1)
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_natural_align_constant_v16i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.1):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 100
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 164
; LEGACY-MESA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load 4, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD2:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 64 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD2]](<16 x s32>), [[LOAD]](p1) :: (volatile store 64 into %ir.cast.out, align 4, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load <16 x i32>, <16 x i32> addrspace(4)* %in.byref
%cast.out = bitcast i32 addrspace(1)* %out to <16 x i32> addrspace(1)*
store volatile <16 x i32> %in, <16 x i32> addrspace(1)* %cast.out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void
}
; Also accept byref kernel arguments with other global address spaces.
define amdgpu_kernel void @byref_global_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* byref(i32) align(4) %in.byref) {
; HSA-VI-LABEL: name: byref_global_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p1) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; HSA-VI: [[COPY1:%[0-9]+]]:_(p1) = COPY [[ADDRSPACE_CAST]](p1)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p1) :: (dereferenceable load 4 from %ir.1, addrspace 1)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_global_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p1) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
; LEGACY-MESA-VI: [[COPY1:%[0-9]+]]:_(p1) = COPY [[ADDRSPACE_CAST]](p1)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p1) :: (dereferenceable load 4 from %ir.1, addrspace 1)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32 addrspace(1)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_flat_i32_arg(i32 addrspace(1)* nocapture %out, i32* byref(i32) align(4) %in.byref) {
; HSA-VI-LABEL: name: byref_flat_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p0) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p0) :: (dereferenceable load 4 from %ir.in.byref)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_flat_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p0) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p0) :: (dereferenceable load 4 from %ir.in.byref)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_constant_32bit_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(6)* byref(i32) align(4) %in.byref) {
; HSA-VI-LABEL: name: byref_constant_32bit_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p6) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p6) :: (dereferenceable load 4 from %ir.in.byref, addrspace 6)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_constant_32bit_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p6) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p6) :: (dereferenceable load 4 from %ir.in.byref, addrspace 6)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32 addrspace(6)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_unknown_as_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(999)* byref(i32) align(4) %in.byref) {
; HSA-VI-LABEL: name: byref_unknown_as_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p999) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p999) :: (dereferenceable load 4 from %ir.in.byref, addrspace 999)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_unknown_as_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p999) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p999) :: (dereferenceable load 4 from %ir.in.byref, addrspace 999)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32 addrspace(999)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4
ret void
}
; Invalid, but should not crash.
define amdgpu_kernel void @byref_local_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(3)* byref(i32) align(4) %in.byref) {
; HSA-VI-LABEL: name: byref_local_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p3) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p3) :: (dereferenceable load 4 from %ir.in.byref, addrspace 3)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_local_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[ADDRSPACE_CAST:%[0-9]+]]:_(p3) = G_ADDRSPACE_CAST [[PTR_ADD1]](p4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[ADDRSPACE_CAST]](p3) :: (dereferenceable load 4 from %ir.in.byref, addrspace 3)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32 addrspace(3)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @multi_byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) align(4) %in0.byref, i32 addrspace(4)* byref(i32) align(4) %in1.byref, i32 %after.offset) {
; HSA-VI-LABEL: name: multi_byref_constant_i32_arg
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 16, addrspace 4)
; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; HSA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; HSA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; HSA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; HSA-VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; HSA-VI: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
; HSA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load 4, align 16, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 4 from %ir.in0.byref, addrspace 4)
; HSA-VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable load 4 from %ir.in1.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD2]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: G_STORE [[LOAD3]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: multi_byref_constant_i32_arg
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load 8, align 4, addrspace 4)
; LEGACY-MESA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44
; LEGACY-MESA-VI: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
; LEGACY-MESA-VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; LEGACY-MESA-VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; LEGACY-MESA-VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 52
; LEGACY-MESA-VI: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64)
; LEGACY-MESA-VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load 4, addrspace 4)
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable load 4 from %ir.in0.byref, addrspace 4)
; LEGACY-MESA-VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable load 4 from %ir.in1.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD2]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[LOAD3]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: G_STORE [[LOAD1]](s32), [[LOAD]](p1) :: (volatile store 4 into %ir.out, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in0 = load i32, i32 addrspace(4)* %in0.byref
%in1 = load i32, i32 addrspace(4)* %in1.byref
store volatile i32 %in0, i32 addrspace(1)* %out, align 4
store volatile i32 %in1, i32 addrspace(1)* %out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void
}
define amdgpu_kernel void @byref_constant_i32_arg_offset0(i32 addrspace(4)* byref(i32) align(4) %in.byref) {
; HSA-VI-LABEL: name: byref_constant_i32_arg_offset0
; HSA-VI: bb.1 (%ir-block.0):
; HSA-VI: liveins: $sgpr4_sgpr5
; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; HSA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; HSA-VI: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; HSA-VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable load 4 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; HSA-VI: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; HSA-VI: S_ENDPGM 0
; LEGACY-MESA-VI-LABEL: name: byref_constant_i32_arg_offset0
; LEGACY-MESA-VI: bb.1 (%ir-block.0):
; LEGACY-MESA-VI: liveins: $sgpr0_sgpr1
; LEGACY-MESA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; LEGACY-MESA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36
; LEGACY-MESA-VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; LEGACY-MESA-VI: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
IR: Have byref imply dereferenceable The langref already states it does, but this wasn't implemented. Also covers inalloca and preallocated. Also helps fix a dependence on pointer element types.
2020-06-26 07:17:24 +08:00
; LEGACY-MESA-VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable load 4 from %ir.in.byref, addrspace 4)
AMDGPU: Start interpreting byref on kernel arguments These are treated identically to value aggregates placed in the kernel argument list. A %struct.foo or %struct.foo addrspace(4)* byref(sizeof(%struct.foo)) align(alignof(%struct.foo)) argument should produce the same offsets and argument metadata. This handles all 3 kernel ABI implementations, and the two HSA metadata emission paths.
2020-05-07 22:47:25 +08:00
; LEGACY-MESA-VI: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; LEGACY-MESA-VI: S_ENDPGM 0
%in = load i32, i32 addrspace(4)* %in.byref
store i32 %in, i32 addrspace(1)* undef, align 4
ret void
}