maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AArch64/variant-pcs.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

52 lines
1.5 KiB
LLVM
Raw Normal View History

[AArch64] Implement .variant_pcs directive A dynamic linker with lazy binding support may need to handle variant PCS function symbols specially, so an ELF symbol table marking STO_AARCH64_VARIANT_PCS [1] was added to address this. Function symbols that follow the vector PCS are marked via the .variant_pcs assembler directive, which takes a single parameter specifying the symbol name and sets the STO_AARCH64_VARIANT_PCS st_other flag in the object file. [1] https://github.com/ARM-software/abi-aa/blob/master/aaelf64/aaelf64.rst#st-other-values Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D89138
2020-10-08 22:51:10 +08:00
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -o - %s | FileCheck %s --check-prefix=CHECK-ASM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -filetype=obj -o - %s \
; RUN: | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-OBJ
define i32 @base_pcs() {
; CHECK-ASM-LABEL: base_pcs:
; CHECK-ASM-NOT: .variant_pcs
; CHECK-OBJ-LABEL: Name: base_pcs
; CHECK-OBJ: Other: 0
ret i32 42
}
define aarch64_vector_pcs <4 x i32> @neon_vector_pcs_1(<4 x i32> %arg) {
; CHECK-ASM: .variant_pcs neon_vector_pcs_1
; CHECK-ASM-NEXT: neon_vector_pcs_1:
; CHECK-OBJ-LABEL: Name: neon_vector_pcs_1
; CHECK-OBJ: Other [ (0x80)
ret <4 x i32> %arg
}
define <vscale x 4 x i32> @sve_vector_pcs_1() {
; CHECK-ASM: .variant_pcs sve_vector_pcs_1
; CHECK-ASM-NEXT: sve_vector_pcs_1:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_1
; CHECK-OBJ: Other [ (0x80)
ret <vscale x 4 x i32> undef
}
define <vscale x 4 x i1> @sve_vector_pcs_2() {
; CHECK-ASM: .variant_pcs sve_vector_pcs_2
; CHECK-ASM-NEXT: sve_vector_pcs_2:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_2
; CHECK-OBJ: Other [ (0x80)
ret <vscale x 4 x i1> undef
}
define void @sve_vector_pcs_3(<vscale x 4 x i32> %arg) {
; CHECK-ASM: .variant_pcs sve_vector_pcs_3
; CHECK-ASM-NEXT: sve_vector_pcs_3:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_3
; CHECK-OBJ: Other [ (0x80)
ret void
}
define void @sve_vector_pcs_4(<vscale x 4 x i1> %arg) {
; CHECK-ASM: .variant_pcs sve_vector_pcs_4
; CHECK-ASM-NEXT: sve_vector_pcs_4:
; CHECK-OBJ-LABEL: Name: sve_vector_pcs_4
; CHECK-OBJ: Other [ (0x80)
ret void
}