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llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-scatter-...

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[AArch64][SVE] NFC: Guard all SVE tests for TypeSize warnings. This patch adds a bunch of CHECK lines to guard against implicit conversions of TypeSize -> uint64_t occuring in code-paths that previously were safe for scalable vectors.
2020-11-03 18:25:06 +08:00
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s 2>%t | FileCheck %s
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
; WARN-NOT: warning
[AArch64][SVE] Add intrinsics for non-temporal scatters/gathers Summary: This patch adds the following intrinsics for non-temporal gather loads and scatter stores: * aarch64_sve_ldnt1_gather_index * aarch64_sve_stnt1_scatter_index These intrinsics implement the "scalar + vector of indices" addressing mode. As opposed to regular and first-faulting gathers/scatters, there's no instruction that would take indices and then scale them. Instead, the indices for non-temporal gathers/scatters are scaled before the intrinsics are lowered to `ldnt1` instructions. The new ISD nodes, GLDNT1_INDEX and SSTNT1_INDEX, are only used as placeholders so that we can easily identify the cases implemented in this patch in performGatherLoadCombine and performScatterStoreCombined. Once encountered, they are replaced with: * GLDNT1_INDEX -> SPLAT_VECTOR + SHL + GLDNT1 * SSTNT1_INDEX -> SPLAT_VECTOR + SHL + SSTNT1 The patterns for lowering ISD::SHL for scalable vectors (required by this patch) were missing, so these are added too. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D75601
2020-03-04 19:21:20 +08:00
;
; STNT1H, STNT1W, STNT1D: base + 64-bit index
; e.g.
; lsl z1.d, z1.d, #1
; stnt1h { z0.d }, p0, [z0.d, x0]
;
define void @sstnt1h_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i16* %base, <vscale x 2 x i64> %offsets) {
; CHECK-LABEL: sstnt1h_index
; CHECK: lsl z1.d, z1.d, #1
; CHECK-NEXT: stnt1h { z0.d }, p0, [z1.d, x0]
; CHECK-NEXT: ret
%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16(<vscale x 2 x i16> %data_trunc,
<vscale x 2 x i1> %pg,
i16* %base,
<vscale x 2 x i64> %offsets)
ret void
}
define void @sstnt1w_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i32* %base, <vscale x 2 x i64> %offsets) {
; CHECK-LABEL: sstnt1w_index
; CHECK: lsl z1.d, z1.d, #2
; CHECK-NEXT: stnt1w { z0.d }, p0, [z1.d, x0]
; CHECK-NEXT: ret
%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32(<vscale x 2 x i32> %data_trunc,
<vscale x 2 x i1> %pg,
i32* %base,
<vscale x 2 x i64> %offsets)
ret void
}
define void @sstnt1d_index(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, i64* %base, <vscale x 2 x i64> %offsets) {
; CHECK-LABEL: sstnt1d_index
; CHECK: lsl z1.d, z1.d, #3
; CHECK-NEXT: stnt1d { z0.d }, p0, [z1.d, x0]
; CHECK-NEXT: ret
call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64(<vscale x 2 x i64> %data,
<vscale x 2 x i1> %pg,
i64* %base,
<vscale x 2 x i64> %offsets)
ret void
}
define void @sstnt1d_index_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, double* %base, <vscale x 2 x i64> %offsets) {
; CHECK-LABEL: sstnt1d_index_double
; CHECK: lsl z1.d, z1.d, #3
; CHECK-NEXT: stnt1d { z0.d }, p0, [z1.d, x0]
; CHECK-NEXT: ret
call void @llvm.aarch64.sve.stnt1.scatter.index.nxv2f64(<vscale x 2 x double> %data,
<vscale x 2 x i1> %pg,
double* %base,
<vscale x 2 x i64> %offsets)
ret void
}
declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i1>, i16*, <vscale x 2 x i64>)
declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32*, <vscale x 2 x i64>)
declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*, <vscale x 2 x i64>)
declare void @llvm.aarch64.sve.stnt1.scatter.index.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*, <vscale x 2 x i64>)