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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir

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[AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode Noticed an unnecessary fallback in arm64-vmul caused by this. Also add a regbankselect test for G_FMA. llvm-svn: 359013
2019-04-24 01:17:06 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect -o - | FileCheck %s
...
---
name: fma_f32
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 4
[AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode Noticed an unnecessary fallback in arm64-vmul caused by this. Also add a regbankselect test for G_FMA. llvm-svn: 359013
2019-04-24 01:17:06 +08:00
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: fma_f32
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s2
[update_mir_test_checks] Handle MI flags properly previously we would generate literal check lines w/ no reg-exps for vregs as MI flags (nsw, ninf, etc.) won't be recognized as a part of MI. Fixing that. Includes updating the MIR tests that suffered from the problem. Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D68905 llvm-svn: 374829
2019-10-15 06:01:58 +08:00
; CHECK: [[FMA:%[0-9]+]]:fpr(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $s0 = COPY [[FMA]](s32)
[AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode Noticed an unnecessary fallback in arm64-vmul caused by this. Also add a regbankselect test for G_FMA. llvm-svn: 359013
2019-04-24 01:17:06 +08:00
; CHECK: RET_ReallyLR implicit $s0
%0:_(s32) = COPY $s0
%1:_(s32) = COPY $s1
%2:_(s32) = COPY $s2
%3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
$s0 = COPY %3(s32)
RET_ReallyLR implicit $s0
...
---
name: fma_f64
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 4
[AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode Noticed an unnecessary fallback in arm64-vmul caused by this. Also add a regbankselect test for G_FMA. llvm-svn: 359013
2019-04-24 01:17:06 +08:00
legalized: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: fma_f64
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d2
[update_mir_test_checks] Handle MI flags properly previously we would generate literal check lines w/ no reg-exps for vregs as MI flags (nsw, ninf, etc.) won't be recognized as a part of MI. Fixing that. Includes updating the MIR tests that suffered from the problem. Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D68905 llvm-svn: 374829
2019-10-15 06:01:58 +08:00
; CHECK: [[FMA:%[0-9]+]]:fpr(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $d0 = COPY [[FMA]](s64)
[AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcode Noticed an unnecessary fallback in arm64-vmul caused by this. Also add a regbankselect test for G_FMA. llvm-svn: 359013
2019-04-24 01:17:06 +08:00
; CHECK: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0
%1:_(s64) = COPY $d1
%2:_(s64) = COPY $d2
%3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
$d0 = COPY %3(s64)
RET_ReallyLR implicit $d0
...