2008-12-09 01:50:35 +08:00
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//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
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2008-11-20 07:18:57 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2008-11-20 07:18:57 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2017-01-28 02:53:00 +08:00
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/// \file This implements the ScheduleDAGInstrs class, which implements
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/// re-scheduling of MachineInstrs.
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2008-11-20 07:18:57 +08:00
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//
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//===----------------------------------------------------------------------===//
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2017-06-06 19:49:48 +08:00
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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2015-12-04 09:51:19 +08:00
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#include "llvm/ADT/IntEqClasses.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/ADT/MapVector.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/ADT/SmallPtrSet.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseSet.h"
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2017-06-06 19:49:48 +08:00
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#include "llvm/ADT/iterator_range.h"
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2020-06-25 21:06:04 +08:00
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#include "llvm/Analysis/AliasAnalysis.h"
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2010-12-16 04:02:24 +08:00
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#include "llvm/Analysis/ValueTracking.h"
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2017-12-13 10:51:04 +08:00
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#include "llvm/CodeGen/LiveIntervals.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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2015-05-09 07:52:00 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2017-06-06 19:49:48 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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2009-09-26 04:36:54 +08:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/CodeGen/MachineOperand.h"
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2008-12-16 11:25:46 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-12-04 09:35:46 +08:00
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#include "llvm/CodeGen/PseudoSourceValue.h"
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2012-06-07 03:47:35 +08:00
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#include "llvm/CodeGen/RegisterPressure.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/CodeGen/ScheduleDAG.h"
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2012-11-28 13:13:24 +08:00
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#include "llvm/CodeGen/ScheduleDFS.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/CodeGen/SlotIndexes.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2018-04-30 22:59:11 +08:00
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#include "llvm/Config/llvm-config.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/IR/Constants.h"
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2016-02-04 01:52:29 +08:00
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#include "llvm/IR/Function.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/Operator.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/Casting.h"
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2012-05-16 02:59:41 +08:00
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#include "llvm/Support/CommandLine.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/Support/Compiler.h"
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2008-11-20 07:18:57 +08:00
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#include "llvm/Support/Debug.h"
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2017-06-02 07:25:02 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2012-10-16 02:02:27 +08:00
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#include "llvm/Support/Format.h"
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2008-11-20 07:18:57 +08:00
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#include "llvm/Support/raw_ostream.h"
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2017-06-02 07:25:02 +08:00
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#include <algorithm>
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#include <cassert>
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#include <iterator>
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#include <string>
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#include <utility>
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#include <vector>
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2013-08-24 01:48:43 +08:00
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2008-11-20 07:18:57 +08:00
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using namespace llvm;
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2017-07-12 06:08:28 +08:00
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#define DEBUG_TYPE "machine-scheduler"
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2014-04-22 10:02:50 +08:00
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2012-05-16 02:59:41 +08:00
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static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
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cl::ZeroOrMore, cl::init(false),
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2015-01-07 21:20:57 +08:00
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cl::desc("Enable use of AA during MI DAG construction"));
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2012-05-16 02:59:41 +08:00
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2014-01-26 03:24:54 +08:00
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static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
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2015-01-07 21:20:57 +08:00
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cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
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2014-01-26 03:24:54 +08:00
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2016-02-04 01:52:29 +08:00
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// Note: the two options below might be used in tuning compile time vs
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// output quality. Setting HugeRegion so large that it will never be
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// reached means best-effort, but may be slow.
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// When Stores and Loads maps (or NonAliasStores and NonAliasLoads)
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// together hold this many SUs, a reduction of maps will be done.
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static cl::opt<unsigned> HugeRegion("dag-maps-huge-region", cl::Hidden,
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cl::init(1000), cl::desc("The limit to use while constructing the DAG "
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"prior to scheduling, at which point a trade-off "
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"is made to avoid excessive compile time."));
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2016-04-16 12:58:30 +08:00
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static cl::opt<unsigned> ReductionSize(
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"dag-maps-reduction-size", cl::Hidden,
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2016-02-04 01:52:29 +08:00
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cl::desc("A huge scheduling region will have maps reduced by this many "
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2016-04-16 12:58:30 +08:00
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"nodes at a time. Defaults to HugeRegion / 2."));
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static unsigned getReductionSize() {
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// Always reduce a huge region with half of the elements, except
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// when user sets this number explicitly.
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if (ReductionSize.getNumOccurrences() == 0)
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return HugeRegion / 2;
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return ReductionSize;
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}
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2016-02-04 01:52:29 +08:00
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static void dumpSUList(ScheduleDAGInstrs::SUList &L) {
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2017-10-15 22:32:27 +08:00
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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2016-02-04 01:52:29 +08:00
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dbgs() << "{ ";
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2016-10-01 07:08:07 +08:00
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for (const SUnit *su : L) {
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2016-02-04 01:52:29 +08:00
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dbgs() << "SU(" << su->NodeNum << ")";
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if (su != L.back())
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dbgs() << ", ";
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}
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dbgs() << "}\n";
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#endif
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}
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2009-01-16 03:20:50 +08:00
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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2014-08-21 03:36:05 +08:00
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const MachineLoopInfo *mli,
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2015-11-03 09:53:29 +08:00
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bool RemoveKillFlags)
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2015-12-05 03:54:24 +08:00
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: ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
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2017-06-02 07:25:02 +08:00
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RemoveKillFlags(RemoveKillFlags),
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2016-02-04 01:52:29 +08:00
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UnknownValue(UndefValue::get(
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2019-03-29 16:33:05 +08:00
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Type::getVoidTy(mf.getFunction().getContext()))), Topo(SUnits, &ExitSU) {
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2011-06-03 04:07:12 +08:00
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DbgValues.clear();
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2012-09-19 02:20:00 +08:00
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2015-01-27 15:54:39 +08:00
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const TargetSubtargetInfo &ST = mf.getSubtarget();
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2018-04-09 03:56:04 +08:00
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SchedModel.init(&ST);
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2009-10-19 03:58:47 +08:00
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}
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2008-11-20 07:18:57 +08:00
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2017-10-12 14:26:04 +08:00
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/// If this machine instr has memory reference information and it can be
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/// tracked to a normal reference to a known object, return the Value
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/// for that object. This function returns false the memory location is
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/// unknown or may alias anything.
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static bool getUnderlyingObjectsForInstr(const MachineInstr *MI,
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2016-07-29 02:40:00 +08:00
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const MachineFrameInfo &MFI,
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2015-03-10 10:37:25 +08:00
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UnderlyingObjectsVector &Objects,
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const DataLayout &DL) {
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2016-04-15 05:31:07 +08:00
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auto allMMOsOkay = [&]() {
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for (const MachineMemOperand *MMO : MI->memoperands()) {
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2019-02-02 06:58:52 +08:00
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// TODO: Figure out whether isAtomic is really necessary (see D57601).
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if (MMO->isVolatile() || MMO->isAtomic())
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2016-04-15 05:31:07 +08:00
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return false;
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if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
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// Function that contain tail calls don't have unique PseudoSourceValue
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// objects. Two PseudoSourceValues might refer to the same or
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// overlapping locations. The client code calling this function assumes
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// this is not the case. So return a conservative answer of no known
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// object.
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2016-07-29 02:40:00 +08:00
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if (MFI.hasTailCall())
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2016-04-15 05:31:07 +08:00
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return false;
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// For now, ignore PseudoSourceValues which may alias LLVM IR values
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// because the code that uses this function has no way to cope with
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// such aliases.
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2016-07-29 02:40:00 +08:00
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if (PSV->isAliased(&MFI))
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2016-04-15 05:31:07 +08:00
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return false;
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2016-07-29 02:40:00 +08:00
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bool MayAlias = PSV->mayAlias(&MFI);
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2016-04-15 05:31:07 +08:00
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Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
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} else if (const Value *V = MMO->getValue()) {
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SmallVector<Value *, 4> Objs;
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2020-07-31 17:09:54 +08:00
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if (!getUnderlyingObjectsForCodeGen(V, Objs))
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2017-10-12 14:26:04 +08:00
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return false;
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2016-04-15 05:31:07 +08:00
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for (Value *V : Objs) {
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2017-08-01 11:32:15 +08:00
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assert(isIdentifiedObject(V));
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2016-04-15 05:31:07 +08:00
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Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
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2016-04-12 23:50:19 +08:00
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}
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2016-04-15 05:31:07 +08:00
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} else
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return false;
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2012-12-11 02:49:16 +08:00
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}
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2016-04-15 05:31:07 +08:00
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return true;
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};
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2017-10-12 14:26:04 +08:00
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if (!allMMOsOkay()) {
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2016-04-15 05:31:07 +08:00
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Objects.clear();
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2017-10-12 14:26:04 +08:00
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return false;
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}
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return true;
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2009-01-30 10:49:14 +08:00
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}
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2012-04-21 04:05:21 +08:00
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void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
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BB = bb;
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2009-02-11 07:27:53 +08:00
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}
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2012-03-08 07:00:49 +08:00
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void ScheduleDAGInstrs::finishBlock() {
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2012-04-21 04:24:33 +08:00
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// Subclasses should no longer refer to the old block.
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2014-04-14 08:51:57 +08:00
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BB = nullptr;
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2012-03-07 13:21:52 +08:00
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}
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void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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2013-08-24 01:48:33 +08:00
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unsigned regioninstrs) {
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2012-04-21 04:05:21 +08:00
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assert(bb == BB && "startBlock should set BB");
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2012-03-09 12:29:02 +08:00
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RegionBegin = begin;
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RegionEnd = end;
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2013-08-24 01:48:33 +08:00
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NumRegionInstrs = regioninstrs;
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2012-03-07 13:21:52 +08:00
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}
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void ScheduleDAGInstrs::exitRegion() {
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// Nothing to do.
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}
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2012-03-08 07:00:49 +08:00
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void ScheduleDAGInstrs::addSchedBarrierDeps() {
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2020-10-15 22:44:50 +08:00
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MachineInstr *ExitMI =
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RegionEnd != BB->end()
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? &*skipDebugInstructionsBackward(RegionEnd, RegionBegin)
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: nullptr;
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2010-10-23 10:10:46 +08:00
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ExitSU.setInstr(ExitMI);
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2016-11-11 09:34:21 +08:00
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// Add dependencies on the defs and uses of the instruction.
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if (ExitMI) {
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2016-10-01 07:08:07 +08:00
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for (const MachineOperand &MO : ExitMI->operands()) {
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2010-10-23 10:10:46 +08:00
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if (!MO.isReg() || MO.isDef()) continue;
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
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Register Reg = MO.getReg();
|
2019-08-02 07:27:28 +08:00
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if (Register::isPhysicalRegister(Reg)) {
|
2013-01-22 02:18:53 +08:00
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|
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
|
2019-08-02 07:27:28 +08:00
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|
} else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
|
2016-10-01 07:08:07 +08:00
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addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
|
2016-11-11 06:11:00 +08:00
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|
}
|
2010-10-23 10:10:46 +08:00
|
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|
}
|
2016-11-11 09:34:21 +08:00
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|
}
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if (!ExitMI || (!ExitMI->isCall() && !ExitMI->isBarrier())) {
|
2010-10-23 10:10:46 +08:00
|
|
|
// For others, e.g. fallthrough, conditional branch, assume the exit
|
2010-10-28 07:17:17 +08:00
|
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|
// uses all the registers that are livein to the successor blocks.
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const MachineBasicBlock *Succ : BB->successors()) {
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|
|
|
for (const auto &LI : Succ->liveins()) {
|
2015-09-10 02:08:03 +08:00
|
|
|
if (!Uses.contains(LI.PhysReg))
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|
|
|
Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
|
2010-10-28 07:17:17 +08:00
|
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|
}
|
2016-10-01 07:08:07 +08:00
|
|
|
}
|
2010-10-23 10:10:46 +08:00
|
|
|
}
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}
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|
2017-01-28 02:53:00 +08:00
|
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|
/// MO is an operand of SU's instruction that defines a physical register. Adds
|
2012-02-23 09:52:38 +08:00
|
|
|
/// data dependencies from SU to any uses of the physical register.
|
2012-08-23 08:39:43 +08:00
|
|
|
void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
|
|
|
|
const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
|
2012-02-23 09:52:38 +08:00
|
|
|
assert(MO.isDef() && "expect physreg def");
|
2012-01-14 10:17:15 +08:00
|
|
|
|
|
|
|
// Ask the target if address-backscheduling is desirable, and if so how much.
|
2015-01-27 15:54:39 +08:00
|
|
|
const TargetSubtargetInfo &ST = MF.getSubtarget();
|
2012-01-14 10:17:15 +08:00
|
|
|
|
2018-10-30 23:04:40 +08:00
|
|
|
// Only use any non-zero latency for real defs/uses, in contrast to
|
|
|
|
// "fake" operands added by regalloc.
|
|
|
|
const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
|
|
|
|
bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() &&
|
|
|
|
!DefMIDesc->hasImplicitDefOfPhysReg(MO.getReg()));
|
2012-06-02 07:28:30 +08:00
|
|
|
for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
|
|
|
|
Alias.isValid(); ++Alias) {
|
2013-01-22 02:18:53 +08:00
|
|
|
for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
|
|
|
|
SUnit *UseSU = I->SU;
|
2012-01-14 10:17:15 +08:00
|
|
|
if (UseSU == SU)
|
|
|
|
continue;
|
2012-10-09 02:54:00 +08:00
|
|
|
|
|
|
|
// Adjust the dependence latency using operand def/use information,
|
|
|
|
// then allow the target to perform its own adjustments.
|
2013-01-22 02:18:53 +08:00
|
|
|
int UseOp = I->OpIdx;
|
2014-04-14 08:51:57 +08:00
|
|
|
MachineInstr *RegUse = nullptr;
|
2012-11-13 03:28:57 +08:00
|
|
|
SDep Dep;
|
|
|
|
if (UseOp < 0)
|
|
|
|
Dep = SDep(SU, SDep::Artificial);
|
|
|
|
else {
|
2013-04-13 14:07:40 +08:00
|
|
|
// Set the hasPhysRegDefs only for physreg defs that have a use within
|
|
|
|
// the scheduling region.
|
|
|
|
SU->hasPhysRegDefs = true;
|
2012-11-13 03:28:57 +08:00
|
|
|
Dep = SDep(SU, SDep::Data, *Alias);
|
|
|
|
RegUse = UseSU->getInstr();
|
|
|
|
}
|
2018-10-30 23:04:40 +08:00
|
|
|
const MCInstrDesc *UseMIDesc =
|
|
|
|
(RegUse ? &UseSU->getInstr()->getDesc() : nullptr);
|
|
|
|
bool ImplicitPseudoUse =
|
|
|
|
(UseMIDesc && UseOp >= ((int)UseMIDesc->getNumOperands()) &&
|
|
|
|
!UseMIDesc->hasImplicitUseOfPhysReg(*Alias));
|
|
|
|
if (!ImplicitPseudoDef && !ImplicitPseudoUse) {
|
|
|
|
Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
|
|
|
|
RegUse, UseOp));
|
2020-03-31 18:57:51 +08:00
|
|
|
ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
|
2020-01-11 04:28:37 +08:00
|
|
|
} else {
|
2018-10-30 23:04:40 +08:00
|
|
|
Dep.setLatency(0);
|
2020-01-11 04:28:37 +08:00
|
|
|
// FIXME: We could always let target to adjustSchedDependency(), and
|
|
|
|
// remove this condition, but that currently asserts in Hexagon BE.
|
|
|
|
if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle()))
|
2020-03-31 18:57:51 +08:00
|
|
|
ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep);
|
2020-01-11 04:28:37 +08:00
|
|
|
}
|
2012-10-09 02:53:57 +08:00
|
|
|
|
2012-11-13 03:28:57 +08:00
|
|
|
UseSU->addPred(Dep);
|
2012-01-14 10:17:15 +08:00
|
|
|
}
|
2012-02-23 09:52:38 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Adds register dependencies (data, anti, and output) from this SUnit
|
2017-01-28 02:53:00 +08:00
|
|
|
/// to following instructions in the same scheduling region that depend the
|
|
|
|
/// physical register referenced at OperIdx.
|
2012-02-23 09:52:38 +08:00
|
|
|
void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
|
2013-12-29 05:56:55 +08:00
|
|
|
MachineInstr *MI = SU->getInstr();
|
|
|
|
MachineOperand &MO = MI->getOperand(OperIdx);
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2016-11-11 07:46:44 +08:00
|
|
|
// We do not need to track any dependencies for constant registers.
|
|
|
|
if (MRI.isConstantPhysReg(Reg))
|
|
|
|
return;
|
2012-02-23 09:52:38 +08:00
|
|
|
|
2020-04-17 23:48:59 +08:00
|
|
|
const TargetSubtargetInfo &ST = MF.getSubtarget();
|
|
|
|
|
2012-02-23 09:52:38 +08:00
|
|
|
// Optionally add output and anti dependencies. For anti
|
|
|
|
// dependencies we use a latency of 0 because for a multi-issue
|
|
|
|
// target we want to allow the defining instruction to issue
|
|
|
|
// in the same cycle as the using instruction.
|
|
|
|
// TODO: Using a latency of 1 here for output dependencies assumes
|
|
|
|
// there's no cost for reusing registers.
|
|
|
|
SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
|
2016-11-11 06:11:00 +08:00
|
|
|
for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
|
2012-02-24 15:04:55 +08:00
|
|
|
if (!Defs.contains(*Alias))
|
2012-02-23 09:52:38 +08:00
|
|
|
continue;
|
2013-01-22 02:18:53 +08:00
|
|
|
for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
|
|
|
|
SUnit *DefSU = I->SU;
|
2012-02-23 09:52:38 +08:00
|
|
|
if (DefSU == &ExitSU)
|
|
|
|
continue;
|
|
|
|
if (DefSU != SU &&
|
|
|
|
(Kind != SDep::Output || !MO.isDead() ||
|
2014-12-05 10:07:35 +08:00
|
|
|
!DefSU->getInstr()->registerDefIsDead(*Alias))) {
|
2020-04-17 23:48:59 +08:00
|
|
|
SDep Dep(SU, Kind, /*Reg=*/*Alias);
|
|
|
|
if (Kind != SDep::Anti)
|
2013-06-15 12:49:57 +08:00
|
|
|
Dep.setLatency(
|
|
|
|
SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
|
2020-04-17 23:48:59 +08:00
|
|
|
ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);
|
|
|
|
DefSU->addPred(Dep);
|
2012-01-14 10:17:15 +08:00
|
|
|
}
|
|
|
|
}
|
2012-02-23 09:52:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!MO.isDef()) {
|
2013-04-13 14:07:40 +08:00
|
|
|
SU->hasPhysRegUses = true;
|
2012-02-23 09:52:38 +08:00
|
|
|
// Either insert a new Reg2SUnits entry with an empty SUnits list, or
|
|
|
|
// retrieve the existing SUnits list for this register's uses.
|
|
|
|
// Push this SUnit on the use list.
|
2016-11-11 06:11:00 +08:00
|
|
|
Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
|
2013-12-29 05:56:55 +08:00
|
|
|
if (RemoveKillFlags)
|
|
|
|
MO.setIsKill(false);
|
2016-11-11 06:11:00 +08:00
|
|
|
} else {
|
2012-08-23 08:39:43 +08:00
|
|
|
addPhysRegDataDeps(SU, OperIdx);
|
2012-01-14 10:17:15 +08:00
|
|
|
|
2018-05-24 16:38:06 +08:00
|
|
|
// Clear previous uses and defs of this register and its subergisters.
|
|
|
|
for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) {
|
|
|
|
if (Uses.contains(*SubReg))
|
|
|
|
Uses.eraseAll(*SubReg);
|
|
|
|
if (!MO.isDead())
|
|
|
|
Defs.eraseAll(*SubReg);
|
|
|
|
}
|
|
|
|
if (MO.isDead() && SU->isCall) {
|
2013-01-22 02:18:53 +08:00
|
|
|
// Calls will not be reordered because of chain dependencies (see
|
|
|
|
// below). Since call operands are dead, calls may continue to be added
|
|
|
|
// to the DefList making dependence checking quadratic in the size of
|
|
|
|
// the block. Instead, we leave only one call at the back of the
|
|
|
|
// DefList.
|
|
|
|
Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
|
|
|
|
Reg2SUnitsMap::iterator B = P.first;
|
|
|
|
Reg2SUnitsMap::iterator I = P.second;
|
|
|
|
for (bool isBegin = I == B; !isBegin; /* empty */) {
|
|
|
|
isBegin = (--I) == B;
|
|
|
|
if (!I->SU->isCall)
|
|
|
|
break;
|
|
|
|
I = Defs.erase(I);
|
|
|
|
}
|
2012-01-14 10:17:15 +08:00
|
|
|
}
|
2013-01-22 02:18:53 +08:00
|
|
|
|
2012-02-23 09:52:38 +08:00
|
|
|
// Defs are pushed in the order they are visited and never reordered.
|
2013-01-22 02:18:53 +08:00
|
|
|
Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
|
2012-01-14 10:17:15 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-04 09:51:19 +08:00
|
|
|
LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
|
|
|
|
{
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2015-12-04 09:51:19 +08:00
|
|
|
// No point in tracking lanemasks if we don't have interesting subregisters.
|
|
|
|
const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
|
|
|
|
if (!RC.HasDisjunctSubRegs)
|
2016-12-15 22:36:06 +08:00
|
|
|
return LaneBitmask::getAll();
|
2015-12-04 09:51:19 +08:00
|
|
|
|
|
|
|
unsigned SubReg = MO.getSubReg();
|
|
|
|
if (SubReg == 0)
|
|
|
|
return RC.getLaneMask();
|
|
|
|
return TRI->getSubRegIndexLaneMask(SubReg);
|
|
|
|
}
|
|
|
|
|
2019-09-20 00:26:14 +08:00
|
|
|
bool ScheduleDAGInstrs::deadDefHasNoUse(const MachineOperand &MO) {
|
|
|
|
auto RegUse = CurrentVRegUses.find(MO.getReg());
|
|
|
|
if (RegUse == CurrentVRegUses.end())
|
|
|
|
return true;
|
|
|
|
return (RegUse->LaneMask & getLaneMaskForMO(MO)).none();
|
|
|
|
}
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Adds register output and data dependencies from this SUnit to instructions
|
|
|
|
/// that occur later in the same scheduling region if they read from or write to
|
|
|
|
/// the virtual register defined at OperIdx.
|
2012-01-14 10:17:18 +08:00
|
|
|
///
|
|
|
|
/// TODO: Hoist loop induction variable increments. This has to be
|
|
|
|
/// reevaluated. Generally, IV scheduling should be done before coalescing.
|
|
|
|
void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
|
2015-12-04 09:51:19 +08:00
|
|
|
MachineInstr *MI = SU->getInstr();
|
|
|
|
MachineOperand &MO = MI->getOperand(OperIdx);
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2015-12-04 09:51:19 +08:00
|
|
|
|
|
|
|
LaneBitmask DefLaneMask;
|
|
|
|
LaneBitmask KillLaneMask;
|
|
|
|
if (TrackLaneMasks) {
|
|
|
|
bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
|
|
|
|
DefLaneMask = getLaneMaskForMO(MO);
|
|
|
|
// If we have a <read-undef> flag, none of the lane values comes from an
|
|
|
|
// earlier instruction.
|
2016-12-15 22:36:06 +08:00
|
|
|
KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask;
|
2015-12-04 09:51:19 +08:00
|
|
|
|
2019-09-20 08:09:15 +08:00
|
|
|
if (MO.getSubReg() != 0 && MO.isUndef()) {
|
|
|
|
// There may be other subregister defs on the same instruction of the same
|
|
|
|
// register in later operands. The lanes of other defs will now be live
|
|
|
|
// after this instruction, so these should not be treated as killed by the
|
|
|
|
// instruction even though they appear to be killed in this one operand.
|
|
|
|
for (int I = OperIdx + 1, E = MI->getNumOperands(); I != E; ++I) {
|
|
|
|
const MachineOperand &OtherMO = MI->getOperand(I);
|
|
|
|
if (OtherMO.isReg() && OtherMO.isDef() && OtherMO.getReg() == Reg)
|
|
|
|
KillLaneMask &= ~getLaneMaskForMO(OtherMO);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-04 09:51:19 +08:00
|
|
|
// Clear undef flag, we'll re-add it later once we know which subregister
|
|
|
|
// Def is first.
|
|
|
|
MO.setIsUndef(false);
|
|
|
|
} else {
|
2016-12-15 22:36:06 +08:00
|
|
|
DefLaneMask = LaneBitmask::getAll();
|
|
|
|
KillLaneMask = LaneBitmask::getAll();
|
2015-12-04 09:51:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (MO.isDead()) {
|
2019-09-20 00:26:14 +08:00
|
|
|
assert(deadDefHasNoUse(MO) && "Dead defs should have no uses");
|
2015-12-04 09:51:19 +08:00
|
|
|
} else {
|
|
|
|
// Add data dependence to all uses we found so far.
|
|
|
|
const TargetSubtargetInfo &ST = MF.getSubtarget();
|
|
|
|
for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
|
|
|
|
E = CurrentVRegUses.end(); I != E; /*empty*/) {
|
|
|
|
LaneBitmask LaneMask = I->LaneMask;
|
|
|
|
// Ignore uses of other lanes.
|
2016-12-15 22:36:06 +08:00
|
|
|
if ((LaneMask & KillLaneMask).none()) {
|
2015-12-04 09:51:19 +08:00
|
|
|
++I;
|
|
|
|
continue;
|
|
|
|
}
|
2012-01-14 10:17:18 +08:00
|
|
|
|
2016-12-17 03:11:56 +08:00
|
|
|
if ((LaneMask & DefLaneMask).any()) {
|
2015-12-04 09:51:19 +08:00
|
|
|
SUnit *UseSU = I->SU;
|
|
|
|
MachineInstr *Use = UseSU->getInstr();
|
|
|
|
SDep Dep(SU, SDep::Data, Reg);
|
|
|
|
Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
|
|
|
|
I->OperandIndex));
|
2020-03-31 18:57:51 +08:00
|
|
|
ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep);
|
2015-12-04 09:51:19 +08:00
|
|
|
UseSU->addPred(Dep);
|
|
|
|
}
|
|
|
|
|
|
|
|
LaneMask &= ~KillLaneMask;
|
|
|
|
// If we found a Def for all lanes of this use, remove it from the list.
|
2016-12-17 03:11:56 +08:00
|
|
|
if (LaneMask.any()) {
|
2015-12-04 09:51:19 +08:00
|
|
|
I->LaneMask = LaneMask;
|
|
|
|
++I;
|
|
|
|
} else
|
|
|
|
I = CurrentVRegUses.erase(I);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Shortcut: Singly defined vregs do not have output/anti dependencies.
|
2012-07-31 07:48:17 +08:00
|
|
|
if (MRI.hasOneDef(Reg))
|
2012-07-28 09:48:15 +08:00
|
|
|
return;
|
2012-02-22 14:08:13 +08:00
|
|
|
|
2015-12-04 09:51:19 +08:00
|
|
|
// Add output dependence to the next nearest defs of this vreg.
|
2012-01-14 10:17:18 +08:00
|
|
|
//
|
|
|
|
// Unless this definition is dead, the output dependence should be
|
|
|
|
// transitively redundant with antidependencies from this definition's
|
|
|
|
// uses. We're conservative for now until we have a way to guarantee the uses
|
|
|
|
// are not eliminated sometime during scheduling. The output dependence edge
|
|
|
|
// is also useful if output latency exceeds def-use latency.
|
2015-12-04 09:51:19 +08:00
|
|
|
LaneBitmask LaneMask = DefLaneMask;
|
|
|
|
for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
|
|
|
|
CurrentVRegDefs.end())) {
|
|
|
|
// Ignore defs for other lanes.
|
2016-12-15 22:36:06 +08:00
|
|
|
if ((V2SU.LaneMask & LaneMask).none())
|
2015-12-04 09:51:19 +08:00
|
|
|
continue;
|
|
|
|
// Add an output dependence.
|
|
|
|
SUnit *DefSU = V2SU.SU;
|
|
|
|
// Ignore additional defs of the same lanes in one instruction. This can
|
|
|
|
// happen because lanemasks are shared for targets with too many
|
|
|
|
// subregisters. We also use some representration tricks/hacks where we
|
|
|
|
// add super-register defs/uses, to imply that although we only access parts
|
|
|
|
// of the reg we care about the full one.
|
|
|
|
if (DefSU == SU)
|
|
|
|
continue;
|
|
|
|
SDep Dep(SU, SDep::Output, Reg);
|
|
|
|
Dep.setLatency(
|
|
|
|
SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
|
|
|
|
DefSU->addPred(Dep);
|
|
|
|
|
|
|
|
// Update current definition. This can get tricky if the def was about a
|
|
|
|
// bigger lanemask before. We then have to shrink it and create a new
|
|
|
|
// VReg2SUnit for the non-overlapping part.
|
|
|
|
LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
|
|
|
|
LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
|
|
|
|
V2SU.SU = SU;
|
|
|
|
V2SU.LaneMask = OverlapMask;
|
2016-12-17 03:11:56 +08:00
|
|
|
if (NonOverlapMask.any())
|
2016-05-25 09:18:00 +08:00
|
|
|
CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
|
2012-01-14 10:17:18 +08:00
|
|
|
}
|
2015-12-04 09:51:19 +08:00
|
|
|
// If there was no CurrentVRegDefs entry for some lanes yet, create one.
|
2016-12-17 03:11:56 +08:00
|
|
|
if (LaneMask.any())
|
2015-12-04 09:51:19 +08:00
|
|
|
CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
|
2012-02-22 14:08:11 +08:00
|
|
|
}
|
2012-01-14 10:17:18 +08:00
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Adds a register data dependency if the instruction that defines the
|
2017-01-28 02:53:00 +08:00
|
|
|
/// virtual register used at OperIdx is mapped to an SUnit. Add a register
|
|
|
|
/// antidependency from this SUnit to instructions that occur later in the same
|
|
|
|
/// scheduling region if they write the virtual register.
|
2012-02-22 14:08:11 +08:00
|
|
|
///
|
|
|
|
/// TODO: Handle ExitSU "uses" properly.
|
|
|
|
void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
|
2015-12-04 09:51:19 +08:00
|
|
|
const MachineInstr *MI = SU->getInstr();
|
2021-04-13 14:51:44 +08:00
|
|
|
assert(!MI->isDebugOrPseudoInstr());
|
2020-10-15 22:44:50 +08:00
|
|
|
|
2015-12-04 09:51:19 +08:00
|
|
|
const MachineOperand &MO = MI->getOperand(OperIdx);
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2015-12-04 09:51:19 +08:00
|
|
|
|
|
|
|
// Remember the use. Data dependencies will be added when we find the def.
|
2016-12-15 22:36:06 +08:00
|
|
|
LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO)
|
|
|
|
: LaneBitmask::getAll();
|
2015-12-04 09:51:19 +08:00
|
|
|
CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
|
|
|
|
|
|
|
|
// Add antidependences to the following defs of the vreg.
|
|
|
|
for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
|
|
|
|
CurrentVRegDefs.end())) {
|
|
|
|
// Ignore defs for unrelated lanes.
|
|
|
|
LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
|
2016-12-15 22:36:06 +08:00
|
|
|
if ((PrevDefLaneMask & LaneMask).none())
|
2015-12-04 09:51:19 +08:00
|
|
|
continue;
|
|
|
|
if (V2SU.SU == SU)
|
|
|
|
continue;
|
2012-02-22 14:08:11 +08:00
|
|
|
|
2015-12-04 09:51:19 +08:00
|
|
|
V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
|
2015-12-03 11:01:10 +08:00
|
|
|
}
|
2012-01-14 10:17:18 +08:00
|
|
|
}
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Returns true if MI is an instruction we are unable to reason about
|
2012-05-16 02:59:41 +08:00
|
|
|
/// (like a call or something with unmodeled side effects).
|
2019-10-19 09:07:48 +08:00
|
|
|
static inline bool isGlobalMemoryObject(AAResults *AA, MachineInstr *MI) {
|
2015-10-25 07:11:13 +08:00
|
|
|
return MI->isCall() || MI->hasUnmodeledSideEffects() ||
|
2016-09-10 09:03:20 +08:00
|
|
|
(MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad(AA));
|
2012-05-16 02:59:41 +08:00
|
|
|
}
|
|
|
|
|
2016-02-04 01:52:29 +08:00
|
|
|
void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
|
|
|
|
unsigned Latency) {
|
2017-03-10 07:33:36 +08:00
|
|
|
if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
|
2016-02-04 01:52:29 +08:00
|
|
|
SDep Dep(SUa, SDep::MayAliasMem);
|
|
|
|
Dep.setLatency(Latency);
|
2012-11-06 11:13:46 +08:00
|
|
|
SUb->addPred(Dep);
|
|
|
|
}
|
2012-05-16 02:59:41 +08:00
|
|
|
}
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Creates an SUnit for each real instruction, numbered in top-down
|
2017-01-28 02:53:00 +08:00
|
|
|
/// topological order. The instruction order A < B, implies that no edge exists
|
|
|
|
/// from B to A.
|
2012-02-22 14:08:11 +08:00
|
|
|
///
|
|
|
|
/// Map each real instruction to its SUnit.
|
|
|
|
///
|
2012-03-14 12:00:41 +08:00
|
|
|
/// After initSUnits, the SUnits vector cannot be resized and the scheduler may
|
|
|
|
/// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
|
|
|
|
/// instead of pointers.
|
|
|
|
///
|
|
|
|
/// MachineScheduler relies on initSUnits numbering the nodes by their order in
|
|
|
|
/// the original instruction list.
|
2012-02-22 14:08:11 +08:00
|
|
|
void ScheduleDAGInstrs::initSUnits() {
|
|
|
|
// We'll be allocating one SUnit for each real instruction in the region,
|
|
|
|
// which is contained within a basic block.
|
2013-08-24 01:48:33 +08:00
|
|
|
SUnits.reserve(NumRegionInstrs);
|
2012-01-14 10:17:18 +08:00
|
|
|
|
2017-06-02 07:25:02 +08:00
|
|
|
for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
|
2021-04-13 14:51:44 +08:00
|
|
|
if (MI.isDebugOrPseudoInstr())
|
2012-02-22 14:08:11 +08:00
|
|
|
continue;
|
2012-01-14 10:17:18 +08:00
|
|
|
|
2016-07-02 00:21:48 +08:00
|
|
|
SUnit *SU = newSUnit(&MI);
|
|
|
|
MISUnitMap[&MI] = SU;
|
2012-02-22 14:08:11 +08:00
|
|
|
|
2016-07-02 00:21:48 +08:00
|
|
|
SU->isCall = MI.isCall();
|
|
|
|
SU->isCommutable = MI.isCommutable();
|
2012-02-22 14:08:11 +08:00
|
|
|
|
|
|
|
// Assign the Latency field of SU using target-provided information.
|
2012-10-10 13:43:09 +08:00
|
|
|
SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
|
2013-12-06 01:55:58 +08:00
|
|
|
|
2014-04-19 01:35:08 +08:00
|
|
|
// If this SUnit uses a reserved or unbuffered resource, mark it as such.
|
|
|
|
//
|
2014-05-15 09:52:21 +08:00
|
|
|
// Reserved resources block an instruction from issuing and stall the
|
2014-04-19 01:35:08 +08:00
|
|
|
// entire pipeline. These are identified by BufferSize=0.
|
|
|
|
//
|
2014-05-15 09:52:21 +08:00
|
|
|
// Unbuffered resources prevent execution of subsequent instructions that
|
2014-04-19 01:35:08 +08:00
|
|
|
// require the same resources. This is used for in-order execution pipelines
|
|
|
|
// within an out-of-order core. These are identified by BufferSize=1.
|
2013-12-06 01:55:58 +08:00
|
|
|
if (SchedModel.hasInstrSchedModel()) {
|
|
|
|
const MCSchedClassDesc *SC = getSchedClass(SU);
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const MCWriteProcResEntry &PRE :
|
|
|
|
make_range(SchedModel.getWriteProcResBegin(SC),
|
|
|
|
SchedModel.getWriteProcResEnd(SC))) {
|
|
|
|
switch (SchedModel.getProcResource(PRE.ProcResourceIdx)->BufferSize) {
|
2013-12-06 01:56:02 +08:00
|
|
|
case 0:
|
|
|
|
SU->hasReservedResource = true;
|
|
|
|
break;
|
|
|
|
case 1:
|
2013-12-06 01:55:58 +08:00
|
|
|
SU->isUnbuffered = true;
|
|
|
|
break;
|
2013-12-06 01:56:02 +08:00
|
|
|
default:
|
|
|
|
break;
|
2013-12-06 01:55:58 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-02-22 14:08:11 +08:00
|
|
|
}
|
2012-01-14 10:17:15 +08:00
|
|
|
}
|
|
|
|
|
2016-02-04 01:52:29 +08:00
|
|
|
class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
|
|
|
|
/// Current total number of SUs in map.
|
2017-06-02 07:25:02 +08:00
|
|
|
unsigned NumNodes = 0;
|
2016-02-04 01:52:29 +08:00
|
|
|
|
|
|
|
/// 1 for loads, 0 for stores. (see comment in SUList)
|
|
|
|
unsigned TrueMemOrderLatency;
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
public:
|
2017-06-02 07:25:02 +08:00
|
|
|
Value2SUsMap(unsigned lat = 0) : TrueMemOrderLatency(lat) {}
|
2016-02-04 01:52:29 +08:00
|
|
|
|
|
|
|
/// To keep NumNodes up to date, insert() is used instead of
|
|
|
|
/// this operator w/ push_back().
|
|
|
|
ValueType &operator[](const SUList &Key) {
|
|
|
|
llvm_unreachable("Don't use. Use insert() instead."); };
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
|
|
|
|
/// reduce().
|
2016-02-04 01:52:29 +08:00
|
|
|
void inline insert(SUnit *SU, ValueType V) {
|
|
|
|
MapVector::operator[](V).push_back(SU);
|
|
|
|
NumNodes++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Clears the list of SUs mapped to V.
|
|
|
|
void inline clearList(ValueType V) {
|
|
|
|
iterator Itr = find(V);
|
|
|
|
if (Itr != end()) {
|
2017-06-02 07:25:02 +08:00
|
|
|
assert(NumNodes >= Itr->second.size());
|
2016-02-04 01:52:29 +08:00
|
|
|
NumNodes -= Itr->second.size();
|
|
|
|
|
|
|
|
Itr->second.clear();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Clears map from all contents.
|
|
|
|
void clear() {
|
|
|
|
MapVector<ValueType, SUList>::clear();
|
|
|
|
NumNodes = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned inline size() const { return NumNodes; }
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Counts the number of SUs in this map after a reduction.
|
2017-06-02 07:25:02 +08:00
|
|
|
void reComputeSize() {
|
2016-02-04 01:52:29 +08:00
|
|
|
NumNodes = 0;
|
|
|
|
for (auto &I : *this)
|
|
|
|
NumNodes += I.second.size();
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned inline getTrueMemOrderLatency() const {
|
|
|
|
return TrueMemOrderLatency;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dump();
|
|
|
|
};
|
|
|
|
|
|
|
|
void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
|
|
|
|
Value2SUsMap &Val2SUsMap) {
|
|
|
|
for (auto &I : Val2SUsMap)
|
|
|
|
addChainDependencies(SU, I.second,
|
|
|
|
Val2SUsMap.getTrueMemOrderLatency());
|
|
|
|
}
|
|
|
|
|
|
|
|
void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
|
|
|
|
Value2SUsMap &Val2SUsMap,
|
|
|
|
ValueType V) {
|
|
|
|
Value2SUsMap::iterator Itr = Val2SUsMap.find(V);
|
|
|
|
if (Itr != Val2SUsMap.end())
|
|
|
|
addChainDependencies(SU, Itr->second,
|
|
|
|
Val2SUsMap.getTrueMemOrderLatency());
|
|
|
|
}
|
|
|
|
|
|
|
|
void ScheduleDAGInstrs::addBarrierChain(Value2SUsMap &map) {
|
2017-06-02 07:25:02 +08:00
|
|
|
assert(BarrierChain != nullptr);
|
2016-02-04 01:52:29 +08:00
|
|
|
|
|
|
|
for (auto &I : map) {
|
|
|
|
SUList &sus = I.second;
|
|
|
|
for (auto *SU : sus)
|
|
|
|
SU->addPredBarrier(BarrierChain);
|
|
|
|
}
|
|
|
|
map.clear();
|
|
|
|
}
|
|
|
|
|
|
|
|
void ScheduleDAGInstrs::insertBarrierChain(Value2SUsMap &map) {
|
2017-06-02 07:25:02 +08:00
|
|
|
assert(BarrierChain != nullptr);
|
2016-02-04 01:52:29 +08:00
|
|
|
|
|
|
|
// Go through all lists of SUs.
|
|
|
|
for (Value2SUsMap::iterator I = map.begin(), EE = map.end(); I != EE;) {
|
|
|
|
Value2SUsMap::iterator CurrItr = I++;
|
|
|
|
SUList &sus = CurrItr->second;
|
|
|
|
SUList::iterator SUItr = sus.begin(), SUEE = sus.end();
|
|
|
|
for (; SUItr != SUEE; ++SUItr) {
|
|
|
|
// Stop on BarrierChain or any instruction above it.
|
|
|
|
if ((*SUItr)->NodeNum <= BarrierChain->NodeNum)
|
|
|
|
break;
|
|
|
|
|
|
|
|
(*SUItr)->addPredBarrier(BarrierChain);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Remove also the BarrierChain from list if present.
|
2016-05-03 01:29:55 +08:00
|
|
|
if (SUItr != SUEE && *SUItr == BarrierChain)
|
2016-02-04 01:52:29 +08:00
|
|
|
SUItr++;
|
|
|
|
|
|
|
|
// Remove all SUs that are now successors of BarrierChain.
|
|
|
|
if (SUItr != sus.begin())
|
|
|
|
sus.erase(sus.begin(), SUItr);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Remove all entries with empty su lists.
|
|
|
|
map.remove_if([&](std::pair<ValueType, SUList> &mapEntry) {
|
|
|
|
return (mapEntry.second.empty()); });
|
|
|
|
|
|
|
|
// Recompute the size of the map (NumNodes).
|
|
|
|
map.reComputeSize();
|
|
|
|
}
|
|
|
|
|
2019-10-19 09:07:48 +08:00
|
|
|
void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
|
2013-08-30 11:49:48 +08:00
|
|
|
RegPressureTracker *RPTracker,
|
2015-12-04 09:51:19 +08:00
|
|
|
PressureDiffs *PDiffs,
|
2016-01-20 08:23:32 +08:00
|
|
|
LiveIntervals *LIS,
|
2015-12-04 09:51:19 +08:00
|
|
|
bool TrackLaneMasks) {
|
2015-01-27 15:54:39 +08:00
|
|
|
const TargetSubtargetInfo &ST = MF.getSubtarget();
|
2013-08-29 11:25:05 +08:00
|
|
|
bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
|
|
|
|
: ST.useAA();
|
2016-02-04 01:52:29 +08:00
|
|
|
AAForDep = UseAA ? AA : nullptr;
|
|
|
|
|
|
|
|
BarrierChain = nullptr;
|
2013-08-29 11:25:05 +08:00
|
|
|
|
2015-12-04 09:51:19 +08:00
|
|
|
this->TrackLaneMasks = TrackLaneMasks;
|
2013-09-05 05:00:02 +08:00
|
|
|
MISUnitMap.clear();
|
|
|
|
ScheduleDAG::clearDAG();
|
|
|
|
|
2012-02-22 14:08:11 +08:00
|
|
|
// Create an SUnit for each real instruction.
|
|
|
|
initSUnits();
|
2008-11-20 07:18:57 +08:00
|
|
|
|
2013-08-30 11:49:48 +08:00
|
|
|
if (PDiffs)
|
|
|
|
PDiffs->init(SUnits.size());
|
|
|
|
|
2016-02-04 01:52:29 +08:00
|
|
|
// We build scheduling units by walking a block's instruction list
|
|
|
|
// from bottom to top.
|
|
|
|
|
|
|
|
// Each MIs' memory operand(s) is analyzed to a list of underlying
|
2016-02-04 21:08:48 +08:00
|
|
|
// objects. The SU is then inserted in the SUList(s) mapped from the
|
|
|
|
// Value(s). Each Value thus gets mapped to lists of SUs depending
|
|
|
|
// on it, stores and loads kept separately. Two SUs are trivially
|
|
|
|
// non-aliasing if they both depend on only identified Values and do
|
|
|
|
// not share any common Value.
|
2016-02-04 01:52:29 +08:00
|
|
|
Value2SUsMap Stores, Loads(1 /*TrueMemOrderLatency*/);
|
|
|
|
|
|
|
|
// Certain memory accesses are known to not alias any SU in Stores
|
|
|
|
// or Loads, and have therefore their own 'NonAlias'
|
|
|
|
// domain. E.g. spill / reload instructions never alias LLVM I/R
|
2016-02-04 21:08:48 +08:00
|
|
|
// Values. It would be nice to assume that this type of memory
|
|
|
|
// accesses always have a proper memory operand modelling, and are
|
|
|
|
// therefore never unanalyzable, but this is conservatively not
|
|
|
|
// done.
|
2016-02-04 01:52:29 +08:00
|
|
|
Value2SUsMap NonAliasStores, NonAliasLoads(1 /*TrueMemOrderLatency*/);
|
|
|
|
|
2019-07-16 23:55:45 +08:00
|
|
|
// Track all instructions that may raise floating-point exceptions.
|
|
|
|
// These do not depend on one other (or normal loads or stores), but
|
|
|
|
// must not be rescheduled across global barriers. Note that we don't
|
|
|
|
// really need a "map" here since we don't track those MIs by value;
|
|
|
|
// using the same Value2SUsMap data type here is simply a matter of
|
|
|
|
// convenience.
|
|
|
|
Value2SUsMap FPExceptions;
|
|
|
|
|
2010-03-11 06:13:47 +08:00
|
|
|
// Remove any stale debug info; sometimes BuildSchedGraph is called again
|
|
|
|
// without emitting the info from the previous call.
|
2011-06-03 04:07:12 +08:00
|
|
|
DbgValues.clear();
|
2014-04-14 08:51:57 +08:00
|
|
|
FirstDbgValue = nullptr;
|
2010-03-11 06:13:47 +08:00
|
|
|
|
2012-02-23 09:52:38 +08:00
|
|
|
assert(Defs.empty() && Uses.empty() &&
|
|
|
|
"Only BuildGraph should update Defs/Uses");
|
2013-01-22 02:18:53 +08:00
|
|
|
Defs.setUniverse(TRI->getNumRegs());
|
|
|
|
Uses.setUniverse(TRI->getNumRegs());
|
2011-05-07 05:52:52 +08:00
|
|
|
|
2015-12-04 09:51:19 +08:00
|
|
|
assert(CurrentVRegDefs.empty() && "nobody else should use CurrentVRegDefs");
|
|
|
|
assert(CurrentVRegUses.empty() && "nobody else should use CurrentVRegUses");
|
|
|
|
unsigned NumVirtRegs = MRI.getNumVirtRegs();
|
|
|
|
CurrentVRegDefs.setUniverse(NumVirtRegs);
|
|
|
|
CurrentVRegUses.setUniverse(NumVirtRegs);
|
|
|
|
|
2012-02-23 09:52:38 +08:00
|
|
|
// Model data dependencies between instructions being scheduled and the
|
|
|
|
// ExitSU.
|
2012-03-08 07:00:49 +08:00
|
|
|
addSchedBarrierDeps();
|
2012-02-23 09:52:38 +08:00
|
|
|
|
2009-02-11 07:27:53 +08:00
|
|
|
// Walk the list of instructions, from bottom moving up.
|
2014-04-14 08:51:57 +08:00
|
|
|
MachineInstr *DbgMI = nullptr;
|
2012-03-09 12:29:02 +08:00
|
|
|
for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
|
2008-11-20 07:18:57 +08:00
|
|
|
MII != MIE; --MII) {
|
2016-07-02 00:21:48 +08:00
|
|
|
MachineInstr &MI = *std::prev(MII);
|
|
|
|
if (DbgMI) {
|
|
|
|
DbgValues.push_back(std::make_pair(DbgMI, &MI));
|
2014-04-14 08:51:57 +08:00
|
|
|
DbgMI = nullptr;
|
2011-06-03 04:07:12 +08:00
|
|
|
}
|
|
|
|
|
2020-10-22 22:47:09 +08:00
|
|
|
if (MI.isDebugValue() || MI.isDebugRef()) {
|
2016-07-02 00:21:48 +08:00
|
|
|
DbgMI = &MI;
|
2010-03-11 06:13:47 +08:00
|
|
|
continue;
|
|
|
|
}
|
2018-05-09 10:42:00 +08:00
|
|
|
if (MI.isDebugLabel())
|
|
|
|
continue;
|
|
|
|
|
2021-04-13 14:51:44 +08:00
|
|
|
if (MI.isPseudoProbe())
|
|
|
|
continue;
|
|
|
|
|
2016-07-02 00:21:48 +08:00
|
|
|
SUnit *SU = MISUnitMap[&MI];
|
2013-08-30 11:49:48 +08:00
|
|
|
assert(SU && "No SUnit mapped to this MI");
|
|
|
|
|
2012-04-25 01:56:43 +08:00
|
|
|
if (RPTracker) {
|
2016-01-13 06:57:35 +08:00
|
|
|
RegisterOperands RegOpers;
|
2016-07-02 00:21:48 +08:00
|
|
|
RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
|
2016-01-20 08:23:32 +08:00
|
|
|
if (TrackLaneMasks) {
|
2016-07-02 00:21:48 +08:00
|
|
|
SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
|
2016-01-20 08:23:32 +08:00
|
|
|
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
|
|
|
|
}
|
2016-01-13 06:57:35 +08:00
|
|
|
if (PDiffs != nullptr)
|
|
|
|
PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
|
|
|
|
|
2017-12-15 11:56:57 +08:00
|
|
|
if (RPTracker->getPos() == RegionEnd || &*RPTracker->getPos() != &MI)
|
|
|
|
RPTracker->recedeSkipDebugValues();
|
2016-07-02 00:21:48 +08:00
|
|
|
assert(&*RPTracker->getPos() == &MI && "RPTracker in sync");
|
2016-01-13 06:57:35 +08:00
|
|
|
RPTracker->recede(RegOpers);
|
2012-04-25 01:56:43 +08:00
|
|
|
}
|
2011-06-03 04:07:12 +08:00
|
|
|
|
2014-03-07 14:08:31 +08:00
|
|
|
assert(
|
2016-07-02 00:21:48 +08:00
|
|
|
(CanHandleTerminators || (!MI.isTerminator() && !MI.isPosition())) &&
|
2014-03-07 14:08:31 +08:00
|
|
|
"Cannot schedule terminators or labels!");
|
2008-11-20 07:18:57 +08:00
|
|
|
|
2008-12-04 09:35:46 +08:00
|
|
|
// Add register-based dependencies (data, anti, and output).
|
2016-05-11 00:50:30 +08:00
|
|
|
// For some instructions (calls, returns, inline-asm, etc.) there can
|
|
|
|
// be explicit uses and implicit defs, in which case the use will appear
|
|
|
|
// on the operand list before the def. Do two passes over the operand
|
|
|
|
// list to make sure that defs are processed before any uses.
|
2012-12-19 04:53:01 +08:00
|
|
|
bool HasVRegDef = false;
|
2016-07-02 00:21:48 +08:00
|
|
|
for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
|
|
|
|
const MachineOperand &MO = MI.getOperand(j);
|
2016-05-11 00:50:30 +08:00
|
|
|
if (!MO.isReg() || !MO.isDef())
|
|
|
|
continue;
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2019-08-02 07:27:28 +08:00
|
|
|
if (Register::isPhysicalRegister(Reg)) {
|
2012-01-14 10:17:15 +08:00
|
|
|
addPhysRegDeps(SU, j);
|
2019-08-02 07:27:28 +08:00
|
|
|
} else if (Register::isVirtualRegister(Reg)) {
|
2016-05-11 00:50:30 +08:00
|
|
|
HasVRegDef = true;
|
|
|
|
addVRegDefDeps(SU, j);
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
}
|
2016-05-11 00:50:30 +08:00
|
|
|
// Now process all uses.
|
2016-07-02 00:21:48 +08:00
|
|
|
for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
|
|
|
|
const MachineOperand &MO = MI.getOperand(j);
|
2016-05-11 04:11:58 +08:00
|
|
|
// Only look at use operands.
|
|
|
|
// We do not need to check for MO.readsReg() here because subsequent
|
|
|
|
// subregister defs will get output dependence edges and need no
|
|
|
|
// additional use dependencies.
|
2016-05-11 00:50:30 +08:00
|
|
|
if (!MO.isReg() || !MO.isUse())
|
|
|
|
continue;
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2019-08-02 07:27:28 +08:00
|
|
|
if (Register::isPhysicalRegister(Reg)) {
|
2016-05-11 00:50:30 +08:00
|
|
|
addPhysRegDeps(SU, j);
|
2019-08-02 07:27:28 +08:00
|
|
|
} else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
|
2016-05-11 00:50:30 +08:00
|
|
|
addVRegUseDeps(SU, j);
|
2016-11-11 06:11:00 +08:00
|
|
|
}
|
2016-05-11 00:50:30 +08:00
|
|
|
}
|
|
|
|
|
2012-12-19 04:53:01 +08:00
|
|
|
// If we haven't seen any uses in this scheduling region, create a
|
|
|
|
// dependence edge to ExitSU to model the live-out latency. This is required
|
|
|
|
// for vreg defs with no in-region use, and prefetches with no vreg def.
|
|
|
|
//
|
|
|
|
// FIXME: NumDataSuccs would be more precise than NumSuccs here. This
|
|
|
|
// check currently relies on being called before adding chain deps.
|
2016-07-02 00:21:48 +08:00
|
|
|
if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
|
2012-12-19 04:53:01 +08:00
|
|
|
SDep Dep(SU, SDep::Artificial);
|
|
|
|
Dep.setLatency(SU->Latency - 1);
|
|
|
|
ExitSU.addPred(Dep);
|
|
|
|
}
|
2008-12-04 09:35:46 +08:00
|
|
|
|
2016-02-04 01:52:29 +08:00
|
|
|
// Add memory dependencies (Note: isStoreToStackSlot and
|
|
|
|
// isLoadFromStackSLot are not usable after stack slots are lowered to
|
|
|
|
// actual addresses).
|
|
|
|
|
|
|
|
// This is a barrier event that acts as a pivotal node in the DAG.
|
2016-07-02 00:21:48 +08:00
|
|
|
if (isGlobalMemoryObject(AA, &MI)) {
|
2016-02-04 01:52:29 +08:00
|
|
|
|
|
|
|
// Become the barrier chain.
|
2009-11-10 03:22:17 +08:00
|
|
|
if (BarrierChain)
|
2016-02-04 01:52:29 +08:00
|
|
|
BarrierChain->addPredBarrier(SU);
|
2009-11-10 03:22:17 +08:00
|
|
|
BarrierChain = SU;
|
2014-12-09 07:36:48 +08:00
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
|
|
|
|
<< BarrierChain->NodeNum << ").\n";);
|
[ScheduleDAGInstrs::buildSchedGraph()] Handling of memory dependecies rewritten.
The buildSchedGraph() was in need of reworking as the AA features had been
added on top of earlier code. It was very difficult to understand, and buggy.
There had been found cases where scheduling dependencies had actually been
missed (see r228686).
AliasChain, RejectMemNodes, adjustChainDeps() and iterateChainSucc() have
been removed. There are instead now just the four maps from Value to SUs, which
have been renamed to Stores, Loads, NonAliasStores and NonAliasLoads.
An unknown store used to become the AliasChain, but now becomes a store mapped
to 'unknownValue' (in Stores). What used to be PendingLoads is instead the
list of SUs mapped to 'unknownValue' in Loads.
RejectMemNodes and adjustChainDeps() used to be a safety-net for everything.
The SU maps were sometimes cleared and SUs were put in RejectMemNodes, where
adjustChainDeps() would look. Instead of this, a more straight forward approach
is used in maintaining the SU maps without clearing them and simply letting
them grow over time. Instead of the cutt-off in adjustChainDeps() search, a
reduction of maps will be done if needed (see below).
Each SUnit either becomes the BarrierChain, or is put into one of the maps. For
each SUnit encountered, all the information about previous ones are still
available until a new BarrierChain is set, at which point the maps are cleared.
For huge regions, the algorithm becomes slow, therefore the maps will get
reduced at a threshold (current default is 1000 nodes), by a fraction (default 1/2).
These values can be tuned by use of CL options in case some test case shows that
they need to be changed (-dag-maps-huge-region and -dag-maps-reduction-size).
There has not been any considerable change observed in output quality or compile
time. There may now be more DAG edges inserted than before (i.e. if A->B->C,
then A->C is not needed). However, in a comparison run there were fewer total
calls to AA, and a somewhat improved compile time, which means this seems to
be not a problem.
http://reviews.llvm.org/D8705
Reviewers: Hal Finkel, Andy Trick.
llvm-svn: 259201
2016-01-30 00:11:18 +08:00
|
|
|
|
2016-02-04 01:52:29 +08:00
|
|
|
// Add dependencies against everything below it and clear maps.
|
|
|
|
addBarrierChain(Stores);
|
|
|
|
addBarrierChain(Loads);
|
|
|
|
addBarrierChain(NonAliasStores);
|
|
|
|
addBarrierChain(NonAliasLoads);
|
2019-07-16 23:55:45 +08:00
|
|
|
addBarrierChain(FPExceptions);
|
2019-06-06 06:33:10 +08:00
|
|
|
|
2016-02-04 01:52:29 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2019-07-16 23:55:45 +08:00
|
|
|
// Instructions that may raise FP exceptions may not be moved
|
|
|
|
// across any global barriers.
|
2019-06-06 06:33:10 +08:00
|
|
|
if (MI.mayRaiseFPException()) {
|
2019-07-16 23:55:45 +08:00
|
|
|
if (BarrierChain)
|
|
|
|
BarrierChain->addPredBarrier(SU);
|
|
|
|
|
|
|
|
FPExceptions.insert(SU, UnknownValue);
|
|
|
|
|
|
|
|
if (FPExceptions.size() >= HugeRegion) {
|
|
|
|
LLVM_DEBUG(dbgs() << "Reducing FPExceptions map.\n";);
|
|
|
|
Value2SUsMap empty;
|
|
|
|
reduceHugeMemNodeMaps(FPExceptions, empty, getReductionSize());
|
|
|
|
}
|
2019-06-06 06:33:10 +08:00
|
|
|
}
|
|
|
|
|
2016-02-04 01:52:29 +08:00
|
|
|
// If it's not a store or a variant load, we're done.
|
2016-09-10 09:03:20 +08:00
|
|
|
if (!MI.mayStore() &&
|
|
|
|
!(MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA)))
|
2016-02-04 01:52:29 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Always add dependecy edge to BarrierChain if present.
|
|
|
|
if (BarrierChain)
|
|
|
|
BarrierChain->addPredBarrier(SU);
|
|
|
|
|
|
|
|
// Find the underlying objects for MI. The Objs vector is either
|
|
|
|
// empty, or filled with the Values of memory locations which this
|
2017-10-12 14:26:04 +08:00
|
|
|
// SU depends on.
|
2016-02-04 01:52:29 +08:00
|
|
|
UnderlyingObjectsVector Objs;
|
2017-10-12 14:26:04 +08:00
|
|
|
bool ObjsFound = getUnderlyingObjectsForInstr(&MI, MFI, Objs,
|
|
|
|
MF.getDataLayout());
|
2016-02-04 01:52:29 +08:00
|
|
|
|
2016-07-02 00:21:48 +08:00
|
|
|
if (MI.mayStore()) {
|
2017-10-12 14:26:04 +08:00
|
|
|
if (!ObjsFound) {
|
2016-02-04 01:52:29 +08:00
|
|
|
// An unknown store depends on all stores and loads.
|
|
|
|
addChainDependencies(SU, Stores);
|
|
|
|
addChainDependencies(SU, NonAliasStores);
|
|
|
|
addChainDependencies(SU, Loads);
|
|
|
|
addChainDependencies(SU, NonAliasLoads);
|
|
|
|
|
|
|
|
// Map this store to 'UnknownValue'.
|
|
|
|
Stores.insert(SU, UnknownValue);
|
2016-04-01 05:55:58 +08:00
|
|
|
} else {
|
|
|
|
// Add precise dependencies against all previously seen memory
|
|
|
|
// accesses mapped to the same Value(s).
|
2016-04-15 05:31:07 +08:00
|
|
|
for (const UnderlyingObject &UnderlObj : Objs) {
|
|
|
|
ValueType V = UnderlObj.getValue();
|
|
|
|
bool ThisMayAlias = UnderlObj.mayAlias();
|
2016-02-04 01:52:29 +08:00
|
|
|
|
2016-04-01 05:55:58 +08:00
|
|
|
// Add dependencies to previous stores and loads mapped to V.
|
2016-04-15 05:31:07 +08:00
|
|
|
addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
|
2016-04-01 05:55:58 +08:00
|
|
|
addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
|
2016-04-12 23:50:19 +08:00
|
|
|
}
|
|
|
|
// Update the store map after all chains have been added to avoid adding
|
|
|
|
// self-loop edge if multiple underlying objects are present.
|
2016-04-15 05:31:07 +08:00
|
|
|
for (const UnderlyingObject &UnderlObj : Objs) {
|
|
|
|
ValueType V = UnderlObj.getValue();
|
|
|
|
bool ThisMayAlias = UnderlObj.mayAlias();
|
2016-02-04 01:52:29 +08:00
|
|
|
|
2016-04-01 05:55:58 +08:00
|
|
|
// Map this store to V.
|
2016-04-15 05:31:07 +08:00
|
|
|
(ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
|
2016-04-01 05:55:58 +08:00
|
|
|
}
|
|
|
|
// The store may have dependencies to unanalyzable loads and
|
|
|
|
// stores.
|
|
|
|
addChainDependencies(SU, Loads, UnknownValue);
|
|
|
|
addChainDependencies(SU, Stores, UnknownValue);
|
2009-11-03 01:06:28 +08:00
|
|
|
}
|
2016-04-01 05:55:58 +08:00
|
|
|
} else { // SU is a load.
|
2017-10-12 14:26:04 +08:00
|
|
|
if (!ObjsFound) {
|
2016-02-04 01:52:29 +08:00
|
|
|
// An unknown load depends on all stores.
|
|
|
|
addChainDependencies(SU, Stores);
|
|
|
|
addChainDependencies(SU, NonAliasStores);
|
|
|
|
|
|
|
|
Loads.insert(SU, UnknownValue);
|
2016-04-01 05:55:58 +08:00
|
|
|
} else {
|
2016-04-15 05:31:07 +08:00
|
|
|
for (const UnderlyingObject &UnderlObj : Objs) {
|
|
|
|
ValueType V = UnderlObj.getValue();
|
|
|
|
bool ThisMayAlias = UnderlObj.mayAlias();
|
2012-12-11 02:49:16 +08:00
|
|
|
|
2016-04-01 05:55:58 +08:00
|
|
|
// Add precise dependencies against all previously seen stores
|
|
|
|
// mapping to the same Value(s).
|
|
|
|
addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
|
2016-02-04 01:52:29 +08:00
|
|
|
|
2016-04-01 05:55:58 +08:00
|
|
|
// Map this load to V.
|
|
|
|
(ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
|
|
|
|
}
|
|
|
|
// The load may have dependencies to unanalyzable stores.
|
|
|
|
addChainDependencies(SU, Stores, UnknownValue);
|
2011-05-06 03:24:06 +08:00
|
|
|
}
|
2016-02-04 01:52:29 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reduce maps if they grow huge.
|
|
|
|
if (Stores.size() + Loads.size() >= HugeRegion) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";);
|
2016-04-16 12:58:30 +08:00
|
|
|
reduceHugeMemNodeMaps(Stores, Loads, getReductionSize());
|
2016-02-04 01:52:29 +08:00
|
|
|
}
|
|
|
|
if (NonAliasStores.size() + NonAliasLoads.size() >= HugeRegion) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(
|
|
|
|
dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";);
|
2016-04-16 12:58:30 +08:00
|
|
|
reduceHugeMemNodeMaps(NonAliasStores, NonAliasLoads, getReductionSize());
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
}
|
2016-02-04 01:52:29 +08:00
|
|
|
|
2012-12-01 09:22:49 +08:00
|
|
|
if (DbgMI)
|
|
|
|
FirstDbgValue = DbgMI;
|
2009-01-16 03:20:50 +08:00
|
|
|
|
2012-02-23 09:52:38 +08:00
|
|
|
Defs.clear();
|
|
|
|
Uses.clear();
|
2015-12-04 09:51:19 +08:00
|
|
|
CurrentVRegDefs.clear();
|
|
|
|
CurrentVRegUses.clear();
|
2019-03-29 16:33:05 +08:00
|
|
|
|
[ScheduleDAGInstrs] Compute topological ordering on demand.
In most cases, the topological ordering does not get changed in
ScheduleDAGInstrs. We can compute the ordering on demand, similar to
D60125.
This drastically cuts down the number of times we need to compute the
topological ordering, e.g. for SPEC2006, SPEC2k and MultiSource, we get
the following stats for -O3 -flto on X86 (showing the top reductions,
with small absolute values filtered). The smallest reduction is -50%.
Slightly positive impact on compile-time (-0.1 % geomean speedup for
test-suite + SPEC & co, with -O1 on X86)
Tests: 243
Metric: pre-RA-sched.NumTopoInits
Program base patch diff
test-suite...ngs-C/fixoutput/fixoutput.test 115.00 3.00 -97.4%
test-suite...ks/Prolangs-C/cdecl/cdecl.test 957.00 26.00 -97.3%
test-suite...math/automotive-basicmath.test 107.00 3.00 -97.2%
test-suite...rolangs-C++/deriv2/deriv2.test 144.00 6.00 -95.8%
test-suite...lowfish/security-blowfish.test 410.00 18.00 -95.6%
test-suite...frame_layout/frame_layout.test 441.00 23.00 -94.8%
test-suite...rolangs-C++/employ/employ.test 159.00 11.00 -93.1%
test-suite...s/Ptrdist/anagram/anagram.test 157.00 11.00 -93.0%
test-suite...s-C/unix-smail/unix-smail.test 829.00 59.00 -92.9%
test-suite...chmarks/Olden/power/power.test 154.00 11.00 -92.9%
test-suite...T95/147.vortex/147.vortex.test 19876.00 1434.00 -92.8%
test-suite...000/255.vortex/255.vortex.test 19881.00 1435.00 -92.8%
test-suite...ce/Applications/Burg/burg.test 2203.00 168.00 -92.4%
test-suite...urce/Applications/hbd/hbd.test 1067.00 85.00 -92.0%
test-suite...ternal/HMMER/hmmcalibrate.test 3145.00 251.00 -92.0%
test-suite.../Applications/spiff/spiff.test 1037.00 84.00 -91.9%
test-suite...SPEC/CINT95/130.li/130.li.test 5913.00 487.00 -91.8%
test-suite.../CINT95/134.perl/134.perl.test 12532.00 1041.00 -91.7%
test-suite...ce/Benchmarks/Olden/bh/bh.test 220.00 19.00 -91.4%
test-suite :: External/Nurbs/nurbs.test 2304.00 206.00 -91.1%
test-suite...arks/VersaBench/dbms/dbms.test 773.00 75.00 -90.3%
test-suite...ce/Applications/siod/siod.test 9043.00 878.00 -90.3%
test-suite...pplications/treecc/treecc.test 4510.00 438.00 -90.3%
test-suite...T2006/456.hmmer/456.hmmer.test 7093.00 697.00 -90.2%
test-suite...s-C/Pathfinder/PathFinder.test 882.00 87.00 -90.1%
test-suite.../CINT2000/176.gcc/176.gcc.test 64978.00 6721.00 -89.7%
test-suite...cations/hexxagon/hexxagon.test 657.00 69.00 -89.5%
test-suite...fice-ispell/office-ispell.test 2712.00 285.00 -89.5%
test-suite.../CINT2006/403.gcc/403.gcc.test 139613.00 14992.00 -89.3%
test-suite...lications/ClamAV/clamscan.test 25880.00 2785.00 -89.2%
Reviewers: MatzeB, atrick, efriedma, niravd
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D60839
llvm-svn: 361253
2019-05-21 21:04:53 +08:00
|
|
|
Topo.MarkDirty();
|
2016-02-04 01:52:29 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
raw_ostream &llvm::operator<<(raw_ostream &OS, const PseudoSourceValue* PSV) {
|
|
|
|
PSV->printCustom(OS);
|
|
|
|
return OS;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ScheduleDAGInstrs::Value2SUsMap::dump() {
|
|
|
|
for (auto &Itr : *this) {
|
|
|
|
if (Itr.first.is<const Value*>()) {
|
|
|
|
const Value *V = Itr.first.get<const Value*>();
|
|
|
|
if (isa<UndefValue>(V))
|
|
|
|
dbgs() << "Unknown";
|
|
|
|
else
|
|
|
|
V->printAsOperand(dbgs());
|
|
|
|
}
|
|
|
|
else if (Itr.first.is<const PseudoSourceValue*>())
|
|
|
|
dbgs() << Itr.first.get<const PseudoSourceValue*>();
|
|
|
|
else
|
|
|
|
llvm_unreachable("Unknown Value type.");
|
|
|
|
|
|
|
|
dbgs() << " : ";
|
|
|
|
dumpSUList(Itr.second);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
|
|
|
|
Value2SUsMap &loads, unsigned N) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n"; stores.dump();
|
|
|
|
dbgs() << "Loading SUnits:\n"; loads.dump());
|
2016-02-04 01:52:29 +08:00
|
|
|
|
|
|
|
// Insert all SU's NodeNums into a vector and sort it.
|
|
|
|
std::vector<unsigned> NodeNums;
|
|
|
|
NodeNums.reserve(stores.size() + loads.size());
|
|
|
|
for (auto &I : stores)
|
|
|
|
for (auto *SU : I.second)
|
|
|
|
NodeNums.push_back(SU->NodeNum);
|
|
|
|
for (auto &I : loads)
|
|
|
|
for (auto *SU : I.second)
|
|
|
|
NodeNums.push_back(SU->NodeNum);
|
llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)
Summary: The convenience wrapper in STLExtras is available since rL342102.
Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb
Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D52573
llvm-svn: 343163
2018-09-27 10:13:45 +08:00
|
|
|
llvm::sort(NodeNums);
|
2016-02-04 01:52:29 +08:00
|
|
|
|
|
|
|
// The N last elements in NodeNums will be removed, and the SU with
|
|
|
|
// the lowest NodeNum of them will become the new BarrierChain to
|
|
|
|
// let the not yet seen SUs have a dependency to the removed SUs.
|
2017-06-02 07:25:02 +08:00
|
|
|
assert(N <= NodeNums.size());
|
2016-02-04 01:52:29 +08:00
|
|
|
SUnit *newBarrierChain = &SUnits[*(NodeNums.end() - N)];
|
|
|
|
if (BarrierChain) {
|
|
|
|
// The aliasing and non-aliasing maps reduce independently of each
|
|
|
|
// other, but share a common BarrierChain. Check if the
|
|
|
|
// newBarrierChain is above the former one. If it is not, it may
|
|
|
|
// introduce a loop to use newBarrierChain, so keep the old one.
|
|
|
|
if (newBarrierChain->NodeNum < BarrierChain->NodeNum) {
|
|
|
|
BarrierChain->addPredBarrier(newBarrierChain);
|
|
|
|
BarrierChain = newBarrierChain;
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Inserting new barrier chain: SU("
|
|
|
|
<< BarrierChain->NodeNum << ").\n";);
|
2016-02-04 01:52:29 +08:00
|
|
|
}
|
|
|
|
else
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Keeping old barrier chain: SU("
|
|
|
|
<< BarrierChain->NodeNum << ").\n";);
|
2016-02-04 01:52:29 +08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
BarrierChain = newBarrierChain;
|
|
|
|
|
|
|
|
insertBarrierChain(stores);
|
|
|
|
insertBarrierChain(loads);
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n"; stores.dump();
|
|
|
|
dbgs() << "Loading SUnits:\n"; loads.dump());
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
|
2017-05-27 10:50:50 +08:00
|
|
|
static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
|
|
|
|
MachineInstr &MI, bool addToLiveRegs) {
|
|
|
|
for (MachineOperand &MO : MI.operands()) {
|
|
|
|
if (!MO.isReg() || !MO.readsReg())
|
|
|
|
continue;
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2017-05-27 10:50:50 +08:00
|
|
|
if (!Reg)
|
|
|
|
continue;
|
2013-12-29 05:56:55 +08:00
|
|
|
|
2017-05-27 10:50:50 +08:00
|
|
|
// Things that are available after the instruction are killed by it.
|
|
|
|
bool IsKill = LiveRegs.available(MRI, Reg);
|
|
|
|
MO.setIsKill(IsKill);
|
2017-06-27 08:58:48 +08:00
|
|
|
if (addToLiveRegs)
|
2017-05-27 10:50:50 +08:00
|
|
|
LiveRegs.addReg(Reg);
|
ScheduleDAGInstrs should toggle kill flags on bundled instrs.
ScheduleDAGInstrs wasn't setting or clearing the kill flags on instructions inside bundles. This led to code such as this
%R3<def> = t2ANDrr %R0
BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use,kill>
t2IT 1, 24, %ITSTATE<imp-def>
R6<def,tied6> = t2ORRrr %R0<kill>, ...
being transformed to
BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use>
t2IT 1, 24, %ITSTATE<imp-def>
R6<def,tied6> = t2ORRrr %R0<kill>, ...
%R3<def> = t2ANDrr %R0<kill>
where the kill flag was removed from the BUNDLE instruction, but not the t2ORRrr inside it. The verifier then thought that
R0 was undefined when read by the AND.
This change make the toggleKillFlags method also check for bundles and toggle flags on bundled instructions.
Setting the kill flag is special cased as we only want to set the kill flag on the last instruction in the bundle.
llvm-svn: 236428
2015-05-05 00:52:06 +08:00
|
|
|
}
|
2013-12-29 05:56:55 +08:00
|
|
|
}
|
|
|
|
|
2017-05-27 10:50:50 +08:00
|
|
|
void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n');
|
2013-12-29 05:56:55 +08:00
|
|
|
|
2017-05-27 10:50:50 +08:00
|
|
|
LiveRegs.init(*TRI);
|
|
|
|
LiveRegs.addLiveOuts(MBB);
|
2013-12-29 05:56:55 +08:00
|
|
|
|
|
|
|
// Examine block from end to start...
|
2017-05-27 10:50:50 +08:00
|
|
|
for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
|
2021-04-13 14:51:44 +08:00
|
|
|
if (MI.isDebugOrPseudoInstr())
|
2013-12-29 05:56:55 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
// Update liveness. Registers that are defed but not used in this
|
|
|
|
// instruction are now dead. Mark register and all subregs as they
|
|
|
|
// are completely defined.
|
2017-05-27 10:50:50 +08:00
|
|
|
for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
|
|
|
|
const MachineOperand &MO = *O;
|
|
|
|
if (MO.isReg()) {
|
|
|
|
if (!MO.isDef())
|
|
|
|
continue;
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2017-05-27 10:50:50 +08:00
|
|
|
if (!Reg)
|
|
|
|
continue;
|
|
|
|
LiveRegs.removeReg(Reg);
|
|
|
|
} else if (MO.isRegMask()) {
|
|
|
|
LiveRegs.removeRegsInMask(MO);
|
2013-12-29 05:56:55 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-27 10:50:50 +08:00
|
|
|
// If there is a bundle header fix it up first.
|
|
|
|
if (!MI.isBundled()) {
|
|
|
|
toggleKills(MRI, LiveRegs, MI, true);
|
|
|
|
} else {
|
2019-07-05 23:32:28 +08:00
|
|
|
MachineBasicBlock::instr_iterator Bundle = MI.getIterator();
|
|
|
|
if (MI.isBundle())
|
2017-05-27 10:50:50 +08:00
|
|
|
toggleKills(MRI, LiveRegs, MI, false);
|
2019-07-05 23:32:28 +08:00
|
|
|
|
2017-05-27 10:50:50 +08:00
|
|
|
// Some targets make the (questionable) assumtion that the instructions
|
|
|
|
// inside the bundle are ordered and consequently only the last use of
|
|
|
|
// a register inside the bundle can kill it.
|
2019-07-05 23:32:28 +08:00
|
|
|
MachineBasicBlock::instr_iterator I = std::next(Bundle);
|
2017-05-27 10:50:50 +08:00
|
|
|
while (I->isBundledWithSucc())
|
|
|
|
++I;
|
|
|
|
do {
|
2021-04-13 14:51:44 +08:00
|
|
|
if (!I->isDebugOrPseudoInstr())
|
2017-05-27 10:50:50 +08:00
|
|
|
toggleKills(MRI, LiveRegs, *I, true);
|
|
|
|
--I;
|
2019-07-05 23:32:28 +08:00
|
|
|
} while (I != Bundle);
|
2013-12-29 05:56:55 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-19 08:23:35 +08:00
|
|
|
void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2018-09-19 08:23:35 +08:00
|
|
|
dumpNodeName(SU);
|
|
|
|
dbgs() << ": ";
|
|
|
|
SU.getInstr()->dump();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void ScheduleDAGInstrs::dump() const {
|
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2020-09-21 19:18:39 +08:00
|
|
|
if (EntrySU.getInstr() != nullptr)
|
|
|
|
dumpNodeAll(EntrySU);
|
2018-09-19 08:23:35 +08:00
|
|
|
for (const SUnit &SU : SUnits)
|
|
|
|
dumpNodeAll(SU);
|
|
|
|
if (ExitSU.getInstr() != nullptr)
|
|
|
|
dumpNodeAll(ExitSU);
|
2012-09-07 03:06:06 +08:00
|
|
|
#endif
|
2008-11-20 07:18:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
|
2014-06-27 06:52:05 +08:00
|
|
|
std::string s;
|
|
|
|
raw_string_ostream oss(s);
|
2020-09-21 19:18:39 +08:00
|
|
|
if (SU == &EntrySU)
|
|
|
|
oss << "<entry>";
|
|
|
|
else if (SU == &ExitSU)
|
2009-02-11 07:27:53 +08:00
|
|
|
oss << "<exit>";
|
|
|
|
else
|
2020-09-20 11:41:25 +08:00
|
|
|
SU->getInstr()->print(oss, /*IsStandalone=*/true);
|
2008-11-20 07:18:57 +08:00
|
|
|
return oss.str();
|
|
|
|
}
|
|
|
|
|
2012-03-07 08:18:22 +08:00
|
|
|
/// Return the basic block label. It is not necessarilly unique because a block
|
|
|
|
/// contains multiple scheduling regions. But it is fine for visualization.
|
|
|
|
std::string ScheduleDAGInstrs::getDAGName() const {
|
|
|
|
return "dag." + BB->getFullName();
|
|
|
|
}
|
2012-10-16 02:02:27 +08:00
|
|
|
|
2019-03-29 16:33:05 +08:00
|
|
|
bool ScheduleDAGInstrs::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
|
|
|
|
return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ScheduleDAGInstrs::addEdge(SUnit *SuccSU, const SDep &PredDep) {
|
|
|
|
if (SuccSU != &ExitSU) {
|
|
|
|
// Do not use WillCreateCycle, it assumes SD scheduling.
|
|
|
|
// If Pred is reachable from Succ, then the edge creates a cycle.
|
|
|
|
if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
|
|
|
|
return false;
|
[ScheduleDAGInstrs] Compute topological ordering on demand.
In most cases, the topological ordering does not get changed in
ScheduleDAGInstrs. We can compute the ordering on demand, similar to
D60125.
This drastically cuts down the number of times we need to compute the
topological ordering, e.g. for SPEC2006, SPEC2k and MultiSource, we get
the following stats for -O3 -flto on X86 (showing the top reductions,
with small absolute values filtered). The smallest reduction is -50%.
Slightly positive impact on compile-time (-0.1 % geomean speedup for
test-suite + SPEC & co, with -O1 on X86)
Tests: 243
Metric: pre-RA-sched.NumTopoInits
Program base patch diff
test-suite...ngs-C/fixoutput/fixoutput.test 115.00 3.00 -97.4%
test-suite...ks/Prolangs-C/cdecl/cdecl.test 957.00 26.00 -97.3%
test-suite...math/automotive-basicmath.test 107.00 3.00 -97.2%
test-suite...rolangs-C++/deriv2/deriv2.test 144.00 6.00 -95.8%
test-suite...lowfish/security-blowfish.test 410.00 18.00 -95.6%
test-suite...frame_layout/frame_layout.test 441.00 23.00 -94.8%
test-suite...rolangs-C++/employ/employ.test 159.00 11.00 -93.1%
test-suite...s/Ptrdist/anagram/anagram.test 157.00 11.00 -93.0%
test-suite...s-C/unix-smail/unix-smail.test 829.00 59.00 -92.9%
test-suite...chmarks/Olden/power/power.test 154.00 11.00 -92.9%
test-suite...T95/147.vortex/147.vortex.test 19876.00 1434.00 -92.8%
test-suite...000/255.vortex/255.vortex.test 19881.00 1435.00 -92.8%
test-suite...ce/Applications/Burg/burg.test 2203.00 168.00 -92.4%
test-suite...urce/Applications/hbd/hbd.test 1067.00 85.00 -92.0%
test-suite...ternal/HMMER/hmmcalibrate.test 3145.00 251.00 -92.0%
test-suite.../Applications/spiff/spiff.test 1037.00 84.00 -91.9%
test-suite...SPEC/CINT95/130.li/130.li.test 5913.00 487.00 -91.8%
test-suite.../CINT95/134.perl/134.perl.test 12532.00 1041.00 -91.7%
test-suite...ce/Benchmarks/Olden/bh/bh.test 220.00 19.00 -91.4%
test-suite :: External/Nurbs/nurbs.test 2304.00 206.00 -91.1%
test-suite...arks/VersaBench/dbms/dbms.test 773.00 75.00 -90.3%
test-suite...ce/Applications/siod/siod.test 9043.00 878.00 -90.3%
test-suite...pplications/treecc/treecc.test 4510.00 438.00 -90.3%
test-suite...T2006/456.hmmer/456.hmmer.test 7093.00 697.00 -90.2%
test-suite...s-C/Pathfinder/PathFinder.test 882.00 87.00 -90.1%
test-suite.../CINT2000/176.gcc/176.gcc.test 64978.00 6721.00 -89.7%
test-suite...cations/hexxagon/hexxagon.test 657.00 69.00 -89.5%
test-suite...fice-ispell/office-ispell.test 2712.00 285.00 -89.5%
test-suite.../CINT2006/403.gcc/403.gcc.test 139613.00 14992.00 -89.3%
test-suite...lications/ClamAV/clamscan.test 25880.00 2785.00 -89.2%
Reviewers: MatzeB, atrick, efriedma, niravd
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D60839
llvm-svn: 361253
2019-05-21 21:04:53 +08:00
|
|
|
Topo.AddPredQueued(SuccSU, PredDep.getSUnit());
|
2019-03-29 16:33:05 +08:00
|
|
|
}
|
|
|
|
SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
|
|
|
|
// Return true regardless of whether a new edge needed to be inserted.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-11-28 13:13:28 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SchedDFSResult Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
namespace llvm {
|
2017-06-02 07:25:02 +08:00
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Internal state used to compute SchedDFSResult.
|
2012-11-28 13:13:28 +08:00
|
|
|
class SchedDFSImpl {
|
|
|
|
SchedDFSResult &R;
|
|
|
|
|
|
|
|
/// Join DAG nodes into equivalence classes by their subtree.
|
|
|
|
IntEqClasses SubtreeClasses;
|
|
|
|
/// List PredSU, SuccSU pairs that represent data edges between subtrees.
|
2017-06-02 07:25:02 +08:00
|
|
|
std::vector<std::pair<const SUnit *, const SUnit*>> ConnectionPairs;
|
2012-11-28 13:13:28 +08:00
|
|
|
|
2013-01-25 14:52:27 +08:00
|
|
|
struct RootData {
|
|
|
|
unsigned NodeID;
|
2017-01-28 02:53:00 +08:00
|
|
|
unsigned ParentNodeID; ///< Parent node (member of the parent subtree).
|
2017-06-02 07:25:02 +08:00
|
|
|
unsigned SubInstrCount = 0; ///< Instr count in this tree only, not
|
|
|
|
/// children.
|
2013-01-25 14:52:27 +08:00
|
|
|
|
|
|
|
RootData(unsigned id): NodeID(id),
|
2017-06-02 07:25:02 +08:00
|
|
|
ParentNodeID(SchedDFSResult::InvalidSubtreeID) {}
|
2013-01-25 14:52:27 +08:00
|
|
|
|
|
|
|
unsigned getSparseSetIndex() const { return NodeID; }
|
|
|
|
};
|
|
|
|
|
|
|
|
SparseSet<RootData> RootSet;
|
|
|
|
|
2012-11-28 13:13:28 +08:00
|
|
|
public:
|
2013-01-25 14:52:27 +08:00
|
|
|
SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
|
|
|
|
RootSet.setUniverse(R.DFSNodeData.size());
|
|
|
|
}
|
2012-11-28 13:13:28 +08:00
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Returns true if this node been visited by the DFS traversal.
|
2013-01-25 14:02:44 +08:00
|
|
|
///
|
|
|
|
/// During visitPostorderNode the Node's SubtreeID is assigned to the Node
|
|
|
|
/// ID. Later, SubtreeID is updated but remains valid.
|
2012-11-28 13:13:28 +08:00
|
|
|
bool isVisited(const SUnit *SU) const {
|
2013-01-25 14:52:27 +08:00
|
|
|
return R.DFSNodeData[SU->NodeNum].SubtreeID
|
|
|
|
!= SchedDFSResult::InvalidSubtreeID;
|
2012-11-28 13:13:28 +08:00
|
|
|
}
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Initializes this node's instruction count. We don't need to flag the node
|
2012-11-28 13:13:28 +08:00
|
|
|
/// visited until visitPostorder because the DAG cannot have cycles.
|
|
|
|
void visitPreorder(const SUnit *SU) {
|
2013-01-25 14:52:27 +08:00
|
|
|
R.DFSNodeData[SU->NodeNum].InstrCount =
|
|
|
|
SU->getInstr()->isTransient() ? 0 : 1;
|
2013-01-25 14:02:44 +08:00
|
|
|
}
|
2012-11-28 13:13:28 +08:00
|
|
|
|
2013-01-25 14:02:44 +08:00
|
|
|
/// Called once for each node after all predecessors are visited. Revisit this
|
|
|
|
/// node's predecessors and potentially join them now that we know the ILP of
|
|
|
|
/// the other predecessors.
|
|
|
|
void visitPostorderNode(const SUnit *SU) {
|
|
|
|
// Mark this node as the root of a subtree. It may be joined with its
|
|
|
|
// successors later.
|
2013-01-25 14:52:27 +08:00
|
|
|
R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
|
|
|
|
RootData RData(SU->NodeNum);
|
|
|
|
RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
|
2012-11-28 13:13:28 +08:00
|
|
|
|
2013-01-25 14:02:44 +08:00
|
|
|
// If any predecessors are still in their own subtree, they either cannot be
|
|
|
|
// joined or are large enough to remain separate. If this parent node's
|
|
|
|
// total instruction count is not greater than a child subtree by at least
|
|
|
|
// the subtree limit, then try to join it now since splitting subtrees is
|
|
|
|
// only useful if multiple high-pressure paths are possible.
|
2013-01-25 14:52:27 +08:00
|
|
|
unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const SDep &PredDep : SU->Preds) {
|
|
|
|
if (PredDep.getKind() != SDep::Data)
|
2013-01-25 14:02:44 +08:00
|
|
|
continue;
|
2016-10-01 07:08:07 +08:00
|
|
|
unsigned PredNum = PredDep.getSUnit()->NodeNum;
|
2013-01-25 14:52:27 +08:00
|
|
|
if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
|
2016-10-01 07:08:07 +08:00
|
|
|
joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
|
2013-01-25 14:52:27 +08:00
|
|
|
|
|
|
|
// Either link or merge the TreeData entry from the child to the parent.
|
2013-01-25 14:52:30 +08:00
|
|
|
if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
|
|
|
|
// If the predecessor's parent is invalid, this is a tree edge and the
|
|
|
|
// current node is the parent.
|
|
|
|
if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
|
|
|
|
RootSet[PredNum].ParentNodeID = SU->NodeNum;
|
|
|
|
}
|
|
|
|
else if (RootSet.count(PredNum)) {
|
|
|
|
// The predecessor is not a root, but is still in the root set. This
|
|
|
|
// must be the new parent that it was just joined to. Note that
|
|
|
|
// RootSet[PredNum].ParentNodeID may either be invalid or may still be
|
|
|
|
// set to the original parent.
|
2013-01-25 14:52:27 +08:00
|
|
|
RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
|
|
|
|
RootSet.erase(PredNum);
|
|
|
|
}
|
2013-01-25 14:02:44 +08:00
|
|
|
}
|
2013-01-25 14:52:27 +08:00
|
|
|
RootSet[SU->NodeNum] = RData;
|
|
|
|
}
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Called once for each tree edge after calling visitPostOrderNode on
|
2017-01-28 02:53:00 +08:00
|
|
|
/// the predecessor. Increment the parent node's instruction count and
|
2013-01-25 14:52:27 +08:00
|
|
|
/// preemptively join this subtree to its parent's if it is small enough.
|
|
|
|
void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
|
|
|
|
R.DFSNodeData[Succ->NodeNum].InstrCount
|
|
|
|
+= R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
|
|
|
|
joinPredSubtree(PredDep, Succ);
|
2012-11-28 13:13:28 +08:00
|
|
|
}
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Adds a connection for cross edges.
|
2013-01-25 14:02:44 +08:00
|
|
|
void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
|
2012-11-28 13:13:28 +08:00
|
|
|
ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
|
|
|
|
}
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Sets each node's subtree ID to the representative ID and record
|
|
|
|
/// connections between trees.
|
2012-11-28 13:13:28 +08:00
|
|
|
void finalize() {
|
|
|
|
SubtreeClasses.compress();
|
2013-01-25 14:52:27 +08:00
|
|
|
R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
|
|
|
|
assert(SubtreeClasses.getNumClasses() == RootSet.size()
|
|
|
|
&& "number of roots should match trees");
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const RootData &Root : RootSet) {
|
|
|
|
unsigned TreeID = SubtreeClasses[Root.NodeID];
|
|
|
|
if (Root.ParentNodeID != SchedDFSResult::InvalidSubtreeID)
|
|
|
|
R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[Root.ParentNodeID];
|
|
|
|
R.DFSTreeData[TreeID].SubInstrCount = Root.SubInstrCount;
|
2013-01-25 14:52:30 +08:00
|
|
|
// Note that SubInstrCount may be greater than InstrCount if we joined
|
|
|
|
// subtrees across a cross edge. InstrCount will be attributed to the
|
|
|
|
// original parent, while SubInstrCount will be attributed to the joined
|
|
|
|
// parent.
|
2013-01-25 14:52:27 +08:00
|
|
|
}
|
2012-11-28 13:13:28 +08:00
|
|
|
R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
|
|
|
|
R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
|
2013-01-25 14:52:27 +08:00
|
|
|
for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
|
|
|
|
R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << " SU(" << Idx << ") in tree "
|
|
|
|
<< R.DFSNodeData[Idx].SubtreeID << '\n');
|
2012-11-28 13:13:28 +08:00
|
|
|
}
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const std::pair<const SUnit*, const SUnit*> &P : ConnectionPairs) {
|
|
|
|
unsigned PredTree = SubtreeClasses[P.first->NodeNum];
|
|
|
|
unsigned SuccTree = SubtreeClasses[P.second->NodeNum];
|
2012-11-28 13:13:28 +08:00
|
|
|
if (PredTree == SuccTree)
|
|
|
|
continue;
|
2016-10-01 07:08:07 +08:00
|
|
|
unsigned Depth = P.first->getDepth();
|
2012-11-28 13:13:28 +08:00
|
|
|
addConnection(PredTree, SuccTree, Depth);
|
|
|
|
addConnection(SuccTree, PredTree, Depth);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
protected:
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Joins the predecessor subtree with the successor that is its DFS parent.
|
|
|
|
/// Applies some heuristics before joining.
|
2013-01-25 14:02:44 +08:00
|
|
|
bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
|
|
|
|
bool CheckLimit = true) {
|
|
|
|
assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
|
|
|
|
|
|
|
|
// Check if the predecessor is already joined.
|
|
|
|
const SUnit *PredSU = PredDep.getSUnit();
|
|
|
|
unsigned PredNum = PredSU->NodeNum;
|
2013-01-25 14:52:27 +08:00
|
|
|
if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
|
2013-01-25 14:02:44 +08:00
|
|
|
return false;
|
2013-01-25 08:12:57 +08:00
|
|
|
|
|
|
|
// Four is the magic number of successors before a node is considered a
|
|
|
|
// pinch point.
|
|
|
|
unsigned NumDataSucs = 0;
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const SDep &SuccDep : PredSU->Succs) {
|
|
|
|
if (SuccDep.getKind() == SDep::Data) {
|
2013-01-25 08:12:57 +08:00
|
|
|
if (++NumDataSucs >= 4)
|
2013-01-25 14:02:44 +08:00
|
|
|
return false;
|
2013-01-25 08:12:57 +08:00
|
|
|
}
|
|
|
|
}
|
2013-01-25 14:52:27 +08:00
|
|
|
if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
|
2013-01-25 14:02:44 +08:00
|
|
|
return false;
|
2013-01-25 14:52:27 +08:00
|
|
|
R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
|
2013-01-25 14:02:44 +08:00
|
|
|
SubtreeClasses.join(Succ->NodeNum, PredNum);
|
|
|
|
return true;
|
2013-01-25 08:12:57 +08:00
|
|
|
}
|
|
|
|
|
2012-11-28 13:13:28 +08:00
|
|
|
/// Called by finalize() to record a connection between trees.
|
|
|
|
void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
|
|
|
|
if (!Depth)
|
|
|
|
return;
|
|
|
|
|
2013-01-25 14:52:27 +08:00
|
|
|
do {
|
|
|
|
SmallVectorImpl<SchedDFSResult::Connection> &Connections =
|
|
|
|
R.SubtreeConnections[FromTree];
|
2016-10-01 07:08:07 +08:00
|
|
|
for (SchedDFSResult::Connection &C : Connections) {
|
|
|
|
if (C.TreeID == ToTree) {
|
|
|
|
C.Level = std::max(C.Level, Depth);
|
2013-01-25 14:52:27 +08:00
|
|
|
return;
|
|
|
|
}
|
2012-11-28 13:13:28 +08:00
|
|
|
}
|
2013-01-25 14:52:27 +08:00
|
|
|
Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
|
|
|
|
FromTree = R.DFSTreeData[FromTree].ParentTreeID;
|
|
|
|
} while (FromTree != SchedDFSResult::InvalidSubtreeID);
|
2012-11-28 13:13:28 +08:00
|
|
|
}
|
|
|
|
};
|
2017-06-02 07:25:02 +08:00
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
} // end namespace llvm
|
2012-11-28 13:13:28 +08:00
|
|
|
|
2012-10-16 02:02:27 +08:00
|
|
|
namespace {
|
2017-06-02 07:25:02 +08:00
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Manage the stack used by a reverse depth-first search over the DAG.
|
2012-10-16 02:02:27 +08:00
|
|
|
class SchedDAGReverseDFS {
|
2017-06-02 07:25:02 +08:00
|
|
|
std::vector<std::pair<const SUnit *, SUnit::const_pred_iterator>> DFSStack;
|
|
|
|
|
2012-10-16 02:02:27 +08:00
|
|
|
public:
|
|
|
|
bool isComplete() const { return DFSStack.empty(); }
|
|
|
|
|
|
|
|
void follow(const SUnit *SU) {
|
|
|
|
DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
|
|
|
|
}
|
|
|
|
void advance() { ++DFSStack.back().second; }
|
|
|
|
|
2012-11-28 13:13:28 +08:00
|
|
|
const SDep *backtrack() {
|
|
|
|
DFSStack.pop_back();
|
2014-04-14 08:51:57 +08:00
|
|
|
return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
|
2012-11-28 13:13:28 +08:00
|
|
|
}
|
2012-10-16 02:02:27 +08:00
|
|
|
|
|
|
|
const SUnit *getCurr() const { return DFSStack.back().first; }
|
|
|
|
|
|
|
|
SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
|
|
|
|
|
|
|
|
SUnit::const_pred_iterator getPredEnd() const {
|
|
|
|
return getCurr()->Preds.end();
|
|
|
|
}
|
|
|
|
};
|
2017-06-02 07:25:02 +08:00
|
|
|
|
|
|
|
} // end anonymous namespace
|
2012-10-16 02:02:27 +08:00
|
|
|
|
2013-01-25 14:02:44 +08:00
|
|
|
static bool hasDataSucc(const SUnit *SU) {
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const SDep &SuccDep : SU->Succs) {
|
|
|
|
if (SuccDep.getKind() == SDep::Data &&
|
|
|
|
!SuccDep.getSUnit()->isBoundaryNode())
|
2013-01-25 14:02:44 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
/// Computes an ILP metric for all nodes in the subDAG reachable via depth-first
|
2012-10-16 02:02:27 +08:00
|
|
|
/// search from this root.
|
2013-01-25 14:33:57 +08:00
|
|
|
void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
|
2012-10-16 02:02:27 +08:00
|
|
|
if (!IsBottomUp)
|
2017-08-04 06:41:12 +08:00
|
|
|
llvm_unreachable("Top-down ILP metric is unimplemented");
|
2012-10-16 02:02:27 +08:00
|
|
|
|
2012-11-28 13:13:28 +08:00
|
|
|
SchedDFSImpl Impl(*this);
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const SUnit &SU : SUnits) {
|
|
|
|
if (Impl.isVisited(&SU) || hasDataSucc(&SU))
|
2013-01-25 14:33:57 +08:00
|
|
|
continue;
|
|
|
|
|
2012-11-28 13:13:28 +08:00
|
|
|
SchedDAGReverseDFS DFS;
|
2016-10-01 07:08:07 +08:00
|
|
|
Impl.visitPreorder(&SU);
|
|
|
|
DFS.follow(&SU);
|
2017-06-02 07:25:02 +08:00
|
|
|
while (true) {
|
2012-11-28 13:13:28 +08:00
|
|
|
// Traverse the leftmost path as far as possible.
|
|
|
|
while (DFS.getPred() != DFS.getPredEnd()) {
|
|
|
|
const SDep &PredDep = *DFS.getPred();
|
|
|
|
DFS.advance();
|
2013-01-25 14:02:44 +08:00
|
|
|
// Ignore non-data edges.
|
2013-01-25 14:52:30 +08:00
|
|
|
if (PredDep.getKind() != SDep::Data
|
|
|
|
|| PredDep.getSUnit()->isBoundaryNode()) {
|
2013-01-25 14:02:44 +08:00
|
|
|
continue;
|
2013-01-25 14:52:30 +08:00
|
|
|
}
|
2013-01-25 14:02:44 +08:00
|
|
|
// An already visited edge is a cross edge, assuming an acyclic DAG.
|
2012-11-28 13:13:28 +08:00
|
|
|
if (Impl.isVisited(PredDep.getSUnit())) {
|
2013-01-25 14:02:44 +08:00
|
|
|
Impl.visitCrossEdge(PredDep, DFS.getCurr());
|
2012-11-28 13:13:28 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
Impl.visitPreorder(PredDep.getSUnit());
|
|
|
|
DFS.follow(PredDep.getSUnit());
|
|
|
|
}
|
|
|
|
// Visit the top of the stack in postorder and backtrack.
|
|
|
|
const SUnit *Child = DFS.getCurr();
|
|
|
|
const SDep *PredDep = DFS.backtrack();
|
2013-01-25 14:02:44 +08:00
|
|
|
Impl.visitPostorderNode(Child);
|
|
|
|
if (PredDep)
|
|
|
|
Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
|
2012-11-28 13:13:28 +08:00
|
|
|
if (DFS.isComplete())
|
|
|
|
break;
|
2012-10-16 02:02:27 +08:00
|
|
|
}
|
2012-11-28 13:13:28 +08:00
|
|
|
}
|
|
|
|
Impl.finalize();
|
|
|
|
}
|
|
|
|
|
|
|
|
/// The root of the given SubtreeID was just scheduled. For all subtrees
|
|
|
|
/// connected to this tree, record the depth of the connection so that the
|
|
|
|
/// nearest connected subtrees can be prioritized.
|
|
|
|
void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
|
2016-10-01 07:08:07 +08:00
|
|
|
for (const Connection &C : SubtreeConnections[SubtreeID]) {
|
|
|
|
SubtreeConnectLevels[C.TreeID] =
|
|
|
|
std::max(SubtreeConnectLevels[C.TreeID], C.Level);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << " Tree: " << C.TreeID << " @"
|
|
|
|
<< SubtreeConnectLevels[C.TreeID] << '\n');
|
2012-10-16 02:02:27 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-15 22:32:27 +08:00
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
2017-01-28 10:02:38 +08:00
|
|
|
LLVM_DUMP_METHOD void ILPValue::print(raw_ostream &OS) const {
|
2012-11-28 13:13:28 +08:00
|
|
|
OS << InstrCount << " / " << Length << " = ";
|
|
|
|
if (!Length)
|
2012-10-16 02:02:27 +08:00
|
|
|
OS << "BADILP";
|
2012-11-28 13:13:28 +08:00
|
|
|
else
|
|
|
|
OS << format("%g", ((double)InstrCount / Length));
|
2012-10-16 02:02:27 +08:00
|
|
|
}
|
|
|
|
|
2017-01-28 10:02:38 +08:00
|
|
|
LLVM_DUMP_METHOD void ILPValue::dump() const {
|
2012-10-16 02:02:27 +08:00
|
|
|
dbgs() << *this << '\n';
|
|
|
|
}
|
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
|
2014-07-02 05:19:13 +08:00
|
|
|
LLVM_DUMP_METHOD
|
2012-10-16 02:02:27 +08:00
|
|
|
raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
|
|
|
|
Val.print(OS);
|
|
|
|
return OS;
|
|
|
|
}
|
|
|
|
|
2017-01-28 02:53:00 +08:00
|
|
|
} // end namespace llvm
|
2017-06-02 07:25:02 +08:00
|
|
|
|
2017-01-28 10:02:38 +08:00
|
|
|
#endif
|