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llvm-project/llvm/test/CodeGen/ARM/cse-libcalls.ll

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ARM: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309755
2017-08-02 06:20:49 +08:00
; RUN: llc < %s | FileCheck %s
Convert a few tests to FileCheck. NFC. llvm-svn: 224705
2014-12-22 21:29:46 +08:00
Re-enable SelectionDAG CSE for calls. It matters in the case of libcalls, as in this testcase on ARM. llvm-svn: 56226
2008-09-16 03:46:03 +08:00
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
ARM: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309755
2017-08-02 06:20:49 +08:00
target triple = "arm-apple-darwin8"
Re-enable SelectionDAG CSE for calls. It matters in the case of libcalls, as in this testcase on ARM. llvm-svn: 56226
2008-09-16 03:46:03 +08:00
; Without CSE of libcalls, there are two calls in the output instead of one.
Convert a few tests to FileCheck. NFC. llvm-svn: 224705
2014-12-22 21:29:46 +08:00
; CHECK: bl ___ltdf
; CHECK-NOT: bl ___ltdf
Do trivial CSE of dead BBs during codegen preparation. Some BBs can become dead after codegen preparation. If we delete them here, it could help enable tail-call optimizations later on. <rdar://problem/10256573> llvm-svn: 152002
2012-03-04 18:46:01 +08:00
define double @u_f_nonbon(double %lambda) nounwind {
Re-enable SelectionDAG CSE for calls. It matters in the case of libcalls, as in this testcase on ARM. llvm-svn: 56226
2008-09-16 03:46:03 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp19.i.i = load double, double* null, align 4 ; <double> [#uses=2]
Re-enable SelectionDAG CSE for calls. It matters in the case of libcalls, as in this testcase on ARM. llvm-svn: 56226
2008-09-16 03:46:03 +08:00
%tmp6.i = fcmp olt double %tmp19.i.i, 1.000000e+00 ; <i1> [#uses=1]
%dielectric.0.i = select i1 %tmp6.i, double 1.000000e+00, double %tmp19.i.i ; <double> [#uses=1]
%tmp10.i4 = fdiv double 0x4074C2D71F36262D, %dielectric.0.i ; <double> [#uses=1]
br i1 false, label %bb28.i, label %bb508.i
bb28.i: ; preds = %bb28.i, %entry
br i1 false, label %bb502.loopexit.i, label %bb28.i
bb.nph53.i: ; preds = %bb502.loopexit.i
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp354.i = fsub double -0.000000e+00, %tmp10.i4 ; <double> [#uses=0]
Re-enable SelectionDAG CSE for calls. It matters in the case of libcalls, as in this testcase on ARM. llvm-svn: 56226
2008-09-16 03:46:03 +08:00
br label %bb244.i
bb244.i: ; preds = %bb244.i, %bb.nph53.i
br label %bb244.i
bb502.loopexit.i: ; preds = %bb28.i
br i1 false, label %bb.nph53.i, label %bb508.i
bb508.i: ; preds = %bb502.loopexit.i, %entry
Do trivial CSE of dead BBs during codegen preparation. Some BBs can become dead after codegen preparation. If we delete them here, it could help enable tail-call optimizations later on. <rdar://problem/10256573> llvm-svn: 152002
2012-03-04 18:46:01 +08:00
ret double %tmp10.i4
Re-enable SelectionDAG CSE for calls. It matters in the case of libcalls, as in this testcase on ARM. llvm-svn: 56226
2008-09-16 03:46:03 +08:00
}