2018-08-03 06:17:53 +08:00
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; RUN: llc -march=hexagon -enable-pipeliner-opt-size -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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2018-03-12 22:01:28 +08:00
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; Test that we generate the correct names for the phis in the kernel for the
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; incoming values. In this case, the loop contains a phi and has another phi
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; as its loop definition, and the two phis are scheduled in different stages.
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;
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; vreg5 = phi(x, vreg4) is scheduled in stage 1, cycle 0
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; vreg4 = phi(y, z) is scheduled in stage 0, cycle 0
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; CHECK-DAG: :[[REG0:[0-9]+]]{{.*}} = {{.*}},#17
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; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: r{{[0-9]+}} = sxth(r[[REG0]])
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; CHECK: endloop0
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; Function Attrs: nounwind optsize
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define void @f0() #0 {
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b0:
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%v0 = getelementptr [8 x i16], [8 x i16]* undef, i32 0, i32 7
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%v1 = bitcast i16* %v0 to [8 x i16]*
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br label %b2
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b1: ; preds = %b2
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unreachable
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b2: ; preds = %b2, %b0
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%v2 = phi i32 [ 7, %b0 ], [ %v11, %b2 ]
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%v3 = phi i16 [ 17, %b0 ], [ %v7, %b2 ]
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%v4 = phi i16 [ 18, %b0 ], [ %v3, %b2 ]
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%v5 = sext i16 %v4 to i32
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%v6 = getelementptr i16, i16* null, i32 -2
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%v7 = load i16, i16* %v6, align 2
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%v8 = sext i16 %v7 to i32
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%v9 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v5, i32 %v8)
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%v10 = trunc i32 %v9 to i16
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store i16 %v10, i16* null, align 2
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%v11 = add nsw i32 %v2, -1
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%v12 = icmp sgt i32 %v11, 1
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br i1 %v12, label %b2, label %b1
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.subsat(i32, i32) #1
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attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readnone }
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