forked from OSchip/llvm-project
28 lines
762 B
LLVM
28 lines
762 B
LLVM
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; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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br label %b1
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b1: ; preds = %b0
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br i1 undef, label %b2, label %b3
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b2: ; preds = %b1
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%v0 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> undef)
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store <32 x i32> %v0, <32 x i32>* undef, align 128
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unreachable
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b3: ; preds = %b1
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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