maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Hexagon/jt-in-text.ll

58 lines
2.3 KiB
LLVM
Raw Normal View History

[Hexagon] Emit jump tables in text section based on a flag This patch adds a new LLVM flag -hexagon-emit-jt-text which is defaulted to "false". The value "true" emits the switch generated jump tables in text section. Differential Revision: https://reviews.llvm.org/D34820 llvm-svn: 306872
2017-07-01 04:21:48 +08:00
; RUN: llc -hexagon-emit-jt-text=true < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown--elf"
; CHECK: .text
; CHECK-NOT: .rodata
; CHECK: .word
@lane0_pwr_st = global i32 0, align 4
@lane1_pwr_st = global i32 0, align 4
@lane2_pwr_st = global i32 0, align 4
@lane3_pwr_st = global i32 0, align 4
; Function Attrs: noinline nounwind
define void @test2(i32 %lane_id, i32 %rx_pwr_st) #0 {
entry:
%lane_id.addr = alloca i32, align 4
%rx_pwr_st.addr = alloca i32, align 4
store i32 %lane_id, i32* %lane_id.addr, align 4
store i32 %rx_pwr_st, i32* %rx_pwr_st.addr, align 4
%0 = load i32, i32* %lane_id.addr, align 4
switch i32 %0, label %sw.epilog [
i32 0, label %sw.bb
i32 1, label %sw.bb1
i32 2, label %sw.bb2
i32 3, label %sw.bb3
i32 15, label %sw.bb4
]
sw.bb: ; preds = %entry
store i32 1, i32* @lane0_pwr_st, align 4
br label %sw.epilog
sw.bb1: ; preds = %entry
store i32 1, i32* @lane1_pwr_st, align 4
br label %sw.epilog
sw.bb2: ; preds = %entry
store i32 1, i32* @lane2_pwr_st, align 4
br label %sw.epilog
sw.bb3: ; preds = %entry
store i32 1, i32* @lane3_pwr_st, align 4
br label %sw.epilog
sw.bb4: ; preds = %entry
store i32 1, i32* @lane0_pwr_st, align 4
store i32 1, i32* @lane1_pwr_st, align 4
store i32 1, i32* @lane2_pwr_st, align 4
store i32 1, i32* @lane3_pwr_st, align 4
br label %sw.epilog
sw.epilog: ; preds = %entry, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
ret void
}
[Hexagon] New HVX target features. This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
2017-10-19 02:07:07 +08:00
attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }