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llvm-project/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll

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[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6 -global-isel %s -o - | FileCheck %s
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
define void @test_void_return() {
; CHECK-LABEL: test_void_return:
; CHECK: bx lr
entry:
ret void
}
[ARM] GlobalISel: Select G_CONSTANT with CImm operands When selecting a G_CONSTANT to a MOVi, we need the value to be an Imm operand. We used to just leave the G_CONSTANT operand unchanged, which works in some cases (such as the GEP offsets that we create when referring to stack slots). However, in many other places the G_CONSTANTs are created with CImm operands. This patch makes sure to handle those as well, and to error out gracefully if in the end we don't end up with an Imm operand. Thanks to Oliver Stannard for reporting this issue. llvm-svn: 301162
2017-04-24 14:30:56 +08:00
define i32 @test_constant_return_i32() {
; CHECK-LABEL: test_constant_return_i32:
; CHECK: mov r0, #42
; CHECK: bx lr
entry:
ret i32 42
}
[ARM] GlobalISel: Support i1 add and ABI extensions Add support for: * i1 add * i1 function arguments, if passed through registers * i1 returns, with ABI signext/zeroext Differential Revision: https://reviews.llvm.org/D27706 llvm-svn: 293035
2017-01-25 16:47:40 +08:00
define zeroext i1 @test_zext_i1(i1 %x) {
; CHECK-LABEL: test_zext_i1
; CHECK: and r0, r0, #1
; CHECK: bx lr
entry:
ret i1 %x
}
define signext i1 @test_sext_i1(i1 %x) {
; CHECK-LABEL: test_sext_i1
[GISel]: Rework legalization algorithm for better elimination of artifacts along with DCE Legalization Artifacts are all those insts that are there to make the type system happy. Currently, the target needs to say all combinations of extends and truncs are legal and there's no way of verifying that post legalization, we only have *truly* legal instructions. This patch changes roughly the legalization algorithm to process all illegal insts at one go, and then process all truncs/extends that were added to satisfy the type constraints separately trying to combine trivial cases until they converge. This has the added benefit that, the target legalizerinfo can only say which truncs and extends are okay and the artifact combiner would combine away other exts and truncs. Updated legalization algorithm to roughly the following pseudo code. WorkList Insts, Artifacts; collect_all_insts_and_artifacts(Insts, Artifacts); do { for (Inst in Insts) legalizeInstrStep(Inst, Insts, Artifacts); for (Artifact in Artifacts) tryCombineArtifact(Artifact, Insts, Artifacts); } while(!Insts.empty()); Also, wrote a simple wrapper equivalent to SetVector, except for erasing, it avoids moving all elements over by one and instead just nulls them out. llvm-svn: 318210
2017-11-15 06:42:19 +08:00
; CHECK: mov r1, #31
; CHECK: lsl r0, r0, r1
; CHECK: asr r0, r0, r1
[ARM] GlobalISel: Support i1 add and ABI extensions Add support for: * i1 add * i1 function arguments, if passed through registers * i1 returns, with ABI signext/zeroext Differential Revision: https://reviews.llvm.org/D27706 llvm-svn: 293035
2017-01-25 16:47:40 +08:00
; CHECK: bx lr
entry:
ret i1 %x
}
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
define zeroext i8 @test_ext_i8(i8 %x) {
; CHECK-LABEL: test_ext_i8:
[globalisel][tablegen] Add support for specific immediates in the match pattern This enables a few rules such as ARM's uxtb instruction. llvm-svn: 319457
2017-12-01 02:48:35 +08:00
; CHECK: uxtb r0, r0
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
; CHECK: bx lr
[GISel]: Rework legalization algorithm for better elimination of artifacts along with DCE Legalization Artifacts are all those insts that are there to make the type system happy. Currently, the target needs to say all combinations of extends and truncs are legal and there's no way of verifying that post legalization, we only have *truly* legal instructions. This patch changes roughly the legalization algorithm to process all illegal insts at one go, and then process all truncs/extends that were added to satisfy the type constraints separately trying to combine trivial cases until they converge. This has the added benefit that, the target legalizerinfo can only say which truncs and extends are okay and the artifact combiner would combine away other exts and truncs. Updated legalization algorithm to roughly the following pseudo code. WorkList Insts, Artifacts; collect_all_insts_and_artifacts(Insts, Artifacts); do { for (Inst in Insts) legalizeInstrStep(Inst, Insts, Artifacts); for (Artifact in Artifacts) tryCombineArtifact(Artifact, Insts, Artifacts); } while(!Insts.empty()); Also, wrote a simple wrapper equivalent to SetVector, except for erasing, it avoids moving all elements over by one and instead just nulls them out. llvm-svn: 318210
2017-11-15 06:42:19 +08:00
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
entry:
ret i8 %x
}
define signext i16 @test_ext_i16(i16 %x) {
; CHECK-LABEL: test_ext_i16:
[GISel]: Rework legalization algorithm for better elimination of artifacts along with DCE Legalization Artifacts are all those insts that are there to make the type system happy. Currently, the target needs to say all combinations of extends and truncs are legal and there's no way of verifying that post legalization, we only have *truly* legal instructions. This patch changes roughly the legalization algorithm to process all illegal insts at one go, and then process all truncs/extends that were added to satisfy the type constraints separately trying to combine trivial cases until they converge. This has the added benefit that, the target legalizerinfo can only say which truncs and extends are okay and the artifact combiner would combine away other exts and truncs. Updated legalization algorithm to roughly the following pseudo code. WorkList Insts, Artifacts; collect_all_insts_and_artifacts(Insts, Artifacts); do { for (Inst in Insts) legalizeInstrStep(Inst, Insts, Artifacts); for (Artifact in Artifacts) tryCombineArtifact(Artifact, Insts, Artifacts); } while(!Insts.empty()); Also, wrote a simple wrapper equivalent to SetVector, except for erasing, it avoids moving all elements over by one and instead just nulls them out. llvm-svn: 318210
2017-11-15 06:42:19 +08:00
; CHECK: mov r1, #16
; CHECK: lsl r0, r0, r1
; CHECK: asr r0, r0, r1
[ARM] GlobalISel: Support i8/i16 ABI extensions At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
2017-01-25 16:10:40 +08:00
; CHECK: bx lr
entry:
ret i16 %x
}
[ARM] GlobalISel: Add support for G_TRUNC Select them as copies. We only select if both the source and the destination are on the same register bank, so this shouldn't cause any trouble. llvm-svn: 300971
2017-04-21 21:16:50 +08:00
define void @test_trunc_i32_i16(i32 %v, i16 *%p) {
; CHECK-LABEL: test_trunc_i32_i16:
; The trunc doesn't result in any instructions, but we
; expect the store to be explicitly 16-bit.
; CHECK: strh r0, [r1]
; CHECK: bx lr
entry:
%v16 = trunc i32 %v to i16
store i16 %v16, i16 *%p
ret void
}
define void @test_trunc_i32_i8(i32 %v, i8 *%p) {
; CHECK-LABEL: test_trunc_i32_i8:
; The trunc doesn't result in any instructions, but we
; expect the store to be explicitly 8-bit.
; CHECK: strb r0, [r1]
; CHECK: bx lr
entry:
%v8 = trunc i32 %v to i8
store i8 %v8, i8 *%p
ret void
}
[ARM] GlobalISel: Lower i8 and i16 register args This allows lowering i8 and i16 arguments if they can fit in the registers. Note that the lowering is incomplete - ABI extensions are handled in a subsequent patch. (Last part of) Differential Revision: https://reviews.llvm.org/D27704 llvm-svn: 290106
2016-12-19 22:08:02 +08:00
define i8 @test_add_i8(i8 %x, i8 %y) {
; CHECK-LABEL: test_add_i8:
; CHECK: add r0, r0, r1
; CHECK: bx lr
entry:
%sum = add i8 %x, %y
ret i8 %sum
}
define i16 @test_add_i16(i16 %x, i16 %y) {
; CHECK-LABEL: test_add_i16:
; CHECK: add r0, r0, r1
; CHECK: bx lr
entry:
%sum = add i16 %x, %y
ret i16 %sum
}
define i32 @test_add_i32(i32 %x, i32 %y) {
; CHECK-LABEL: test_add_i32:
[ARM] GlobalISel: Select add i32, i32 Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
2016-12-16 20:54:46 +08:00
; CHECK: add r0, r0, r1
; CHECK: bx lr
entry:
%sum = add i32 %x, %y
ret i32 %sum
}
[ARM] GlobalISel: Lower more than 4 arguments This adds support for lowering more than 4 arguments (although still i32 only). It uses the handleAssignments / ValueHandler infrastructure extracted from the AArch64 backend in r288658. Differential Revision: https://reviews.llvm.org/D27195 llvm-svn: 290098
2016-12-19 19:55:41 +08:00
[ARM] GlobalISel: Add support for G_SUB Support G_SUB throughout the GlobalISel pipeline. It is exactly the same as G_ADD, nothing fancy. llvm-svn: 300546
2017-04-18 20:35:28 +08:00
define i8 @test_sub_i8(i8 %x, i8 %y) {
; CHECK-LABEL: test_sub_i8:
; CHECK: sub r0, r0, r1
; CHECK: bx lr
entry:
%sum = sub i8 %x, %y
ret i8 %sum
}
define i16 @test_sub_i16(i16 %x, i16 %y) {
; CHECK-LABEL: test_sub_i16:
; CHECK: sub r0, r0, r1
; CHECK: bx lr
entry:
%sum = sub i16 %x, %y
ret i16 %sum
}
define i32 @test_sub_i32(i32 %x, i32 %y) {
; CHECK-LABEL: test_sub_i32:
; CHECK: sub r0, r0, r1
; CHECK: bx lr
entry:
%sum = sub i32 %x, %y
ret i32 %sum
}
[ARM] GlobalISel: Add support for G_MUL Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
2017-04-19 15:29:46 +08:00
define i8 @test_mul_i8(i8 %x, i8 %y) {
; CHECK-LABEL: test_mul_i8:
; CHECK: mul r0, r0, r1
; CHECK: bx lr
entry:
%sum = mul i8 %x, %y
ret i8 %sum
}
define i16 @test_mul_i16(i16 %x, i16 %y) {
; CHECK-LABEL: test_mul_i16:
; CHECK: mul r0, r0, r1
; CHECK: bx lr
entry:
%sum = mul i16 %x, %y
ret i16 %sum
}
define i32 @test_mul_i32(i32 %x, i32 %y) {
; CHECK-LABEL: test_mul_i32:
; CHECK: mul r0, r0, r1
; CHECK: bx lr
entry:
%sum = mul i32 %x, %y
ret i32 %sum
}
[ARM] GlobalISel: Support G_AND This is identical to the support for the other binary operators: - widen to s32 - map into GPR - select ANDrr (via TableGen'erated code) llvm-svn: 304885
2017-06-07 17:17:41 +08:00
define i8 @test_and_i8(i8 %x, i8 %y) {
; CHECK-LABEL: test_and_i8:
; CHECK: and r0, r0, r1
; CHECK: bx lr
entry:
%sum = and i8 %x, %y
ret i8 %sum
}
define i16 @test_and_i16(i16 %x, i16 %y) {
; CHECK-LABEL: test_and_i16:
; CHECK: and r0, r0, r1
; CHECK: bx lr
entry:
%sum = and i16 %x, %y
ret i16 %sum
}
define i32 @test_and_i32(i32 %x, i32 %y) {
; CHECK-LABEL: test_and_i32:
; CHECK: and r0, r0, r1
; CHECK: bx lr
entry:
%sum = and i32 %x, %y
ret i32 %sum
}
[ARM] GlobalISel: Support G_OR Same as the other binary operators: - legalize to 32 bits - map to GPRs - select ORRrr thanks to TableGen'erated code llvm-svn: 304890
2017-06-07 18:14:23 +08:00
define i8 @test_or_i8(i8 %x, i8 %y) {
; CHECK-LABEL: test_or_i8:
; CHECK: orr r0, r0, r1
; CHECK: bx lr
entry:
%sum = or i8 %x, %y
ret i8 %sum
}
define i16 @test_or_i16(i16 %x, i16 %y) {
; CHECK-LABEL: test_or_i16:
; CHECK: orr r0, r0, r1
; CHECK: bx lr
entry:
%sum = or i16 %x, %y
ret i16 %sum
}
define i32 @test_or_i32(i32 %x, i32 %y) {
; CHECK-LABEL: test_or_i32:
; CHECK: orr r0, r0, r1
; CHECK: bx lr
entry:
%sum = or i32 %x, %y
ret i32 %sum
}
[ARM] GlobalISel: Support G_XOR Same as the other binary operators: - legalize to 32 bits - map to GPRs - select to EORrr via TableGen'erated code llvm-svn: 304898
2017-06-07 19:57:30 +08:00
define i8 @test_xor_i8(i8 %x, i8 %y) {
; CHECK-LABEL: test_xor_i8:
; CHECK: eor r0, r0, r1
; CHECK: bx lr
entry:
%sum = xor i8 %x, %y
ret i8 %sum
}
define i16 @test_xor_i16(i16 %x, i16 %y) {
; CHECK-LABEL: test_xor_i16:
; CHECK: eor r0, r0, r1
; CHECK: bx lr
entry:
%sum = xor i16 %x, %y
ret i16 %sum
}
define i32 @test_xor_i32(i32 %x, i32 %y) {
; CHECK-LABEL: test_xor_i32:
; CHECK: eor r0, r0, r1
; CHECK: bx lr
entry:
%sum = xor i32 %x, %y
ret i32 %sum
}
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
define i32 @test_stack_args_i32(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
; CHECK-LABEL: test_stack_args_i32:
[ARM] GlobalISel: Lower more than 4 arguments This adds support for lowering more than 4 arguments (although still i32 only). It uses the handleAssignments / ValueHandler infrastructure extracted from the AArch64 backend in r288658. Differential Revision: https://reviews.llvm.org/D27195 llvm-svn: 290098
2016-12-19 19:55:41 +08:00
; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
; CHECK: ldr [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
; CHECK: add r0, r2, [[P5]]
; CHECK: bx lr
entry:
%sum = add i32 %p2, %p5
ret i32 %sum
}
[ARM] GlobalISel: Load i1, i8 and i16 args from stack Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
2017-01-26 17:20:47 +08:00
define i16 @test_stack_args_mixed(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4, i16 %p5) {
; CHECK-LABEL: test_stack_args_mixed:
; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
; CHECK: ldrh [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
; CHECK: add r0, r1, [[P5]]
; CHECK: bx lr
entry:
%sum = add i16 %p1, %p5
ret i16 %sum
}
define i16 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i16 zeroext %p4) {
; CHECK-LABEL: test_stack_args_zeroext:
; CHECK: mov [[P4ADDR:r[0-9]+]], sp
; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
; CHECK: add r0, r1, [[P4]]
; CHECK: bx lr
entry:
%sum = add i16 %p1, %p4
ret i16 %sum
}
define i8 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 signext %p4) {
; CHECK-LABEL: test_stack_args_signext:
; CHECK: mov [[P4ADDR:r[0-9]+]], sp
; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
; CHECK: add r0, r2, [[P4]]
; CHECK: bx lr
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
}
[ARM] GlobalISel: Lower pointer args and returns It is important to change the ArgInfo's type from pointer to integer, otherwise the CC assign function won't know what to do. Instead of hacking it up, we use ComputeValueVTs and introduce some of the helpers that we will need later on for lowering more complex types. llvm-svn: 293889
2017-02-02 22:01:00 +08:00
[ARM] GlobalISel: Fix extended stack operands Fix a crash when trying to extend a value passed as a sign- or zero-extended stack parameter. The cause of the crash was that we were setting the size of the loaded value to 32 bits, and then tyring to extend again to 32 bits. This patch addresses the issue by also introducing a G_TRUNC after the load. This will leave the unused bits to their original values set by the caller, while being consistent about the types. For values that are not extended, we just use a smaller load. llvm-svn: 301531
2017-04-27 18:23:30 +08:00
define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4) {
; CHECK-LABEL: test_stack_args_noext:
; CHECK: mov [[P4ADDR:r[0-9]+]], sp
; CHECK: ldrb [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
; CHECK: add r0, r2, [[P4]]
; CHECK: bx lr
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
}
[ARM] GlobalISel: Lower pointer args and returns It is important to change the ArgInfo's type from pointer to integer, otherwise the CC assign function won't know what to do. Instead of hacking it up, we use ComputeValueVTs and introduce some of the helpers that we will need later on for lowering more complex types. llvm-svn: 293889
2017-02-02 22:01:00 +08:00
define i32 @test_ptr_arg_in_reg(i32* %p) {
; CHECK-LABEL: test_ptr_arg_in_reg:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
%v = load i32, i32* %p
ret i32 %v
}
define i32 @test_ptr_arg_on_stack(i32 %f0, i32 %f1, i32 %f2, i32 %f3, i32* %p) {
; CHECK-LABEL: test_ptr_arg_on_stack:
; CHECK: mov r0, sp
; CHECK: ldr r0, [r0]
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
%v = load i32, i32* %p
ret i32 %v
}
define i8* @test_ptr_ret(i8** %p) {
; CHECK-LABEL: test_ptr_ret:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
entry:
%v = load i8*, i8** %p
ret i8* %v
}
[ARM] GlobalISel: Lower single precision FP args Both for aapcscc and aapcs_vfpcc. We currently filter out soft float targets because we don't support libcalls yet. llvm-svn: 294584
2017-02-09 21:09:59 +08:00
define arm_aapcs_vfpcc float @test_float_hard(float %f0, float %f1) {
; CHECK-LABEL: test_float_hard:
; CHECK: vadd.f32 s0, s0, s1
; CHECK: bx lr
entry:
%v = fadd float %f0, %f1
ret float %v
}
define arm_aapcscc float @test_float_softfp(float %f0, float %f1) {
; CHECK-LABEL: test_float_softfp:
; CHECK-DAG: vmov [[F0:s[0-9]+]], r0
; CHECK-DAG: vmov [[F1:s[0-9]+]], r1
; CHECK: vadd.f32 [[FV:s[0-9]+]], [[F0]], [[F1]]
; CHECK: vmov r0, [[FV]]
; CHECK: bx lr
entry:
%v = fadd float %f0, %f1
ret float %v
}
[ARM] GlobalISel: Add end-to-end tests for double Test some really basic functionality through the whole GlobalISel pipeline. llvm-svn: 295438
2017-02-17 19:25:11 +08:00
define arm_aapcs_vfpcc double @test_double_hard(double %f0, double %f1) {
; CHECK-LABEL: test_double_hard:
; CHECK: vadd.f64 d0, d0, d1
; CHECK: bx lr
entry:
%v = fadd double %f0, %f1
ret double %v
}
define arm_aapcscc double @test_double_softfp(double %f0, double %f1) {
; CHECK-LABEL: test_double_softfp:
; CHECK-DAG: vmov [[F0:d[0-9]+]], r0, r1
; CHECK-DAG: vmov [[F1:d[0-9]+]], r2, r3
; CHECK: vadd.f64 [[FV:d[0-9]+]], [[F0]], [[F1]]
[ARM] GlobalISel: Purge G_SEQUENCE According to the commit message from r296921, G_MERGE_VALUES and G_INSERT are to be preferred over G_SEQUENCE. Therefore, stop generating G_SEQUENCE in the ARM backend and remove the code dealing with it. This boils down to the code breaking up double values for the soft float calling convention. Use G_MERGE_VALUES + G_UNMERGE_VALUES instead of G_SEQUENCE + G_EXTRACT for it. This maps very nicely to VMOVDRR + VMOVRRD and simplifies the code in the instruction selector. There's one occurence of G_SEQUENCE left in arm-irtranslator.ll, but that is part of the target-independent code for translating constant structs. Therefore, it is beyond the scope of this commit. llvm-svn: 304902
2017-06-07 20:35:05 +08:00
; CHECK: vmov r0, r1, [[FV]]
[ARM] GlobalISel: Add end-to-end tests for double Test some really basic functionality through the whole GlobalISel pipeline. llvm-svn: 295438
2017-02-17 19:25:11 +08:00
; CHECK: bx lr
entry:
%v = fadd double %f0, %f1
ret double %v
}
[ARM] GlobalISel: Support G_ICMP for i32 and pointers Add support throughout the pipeline: - mark as legal for s32 and pointers - map to GPRs - lower to a sequence of instructions, which moves 0 or 1 into the result register based on the flags set by a CMPrr We have copied from FastISel a helper function which maps CmpInst predicates into ARMCC codes. Ideally, we should be able to move it somewhere that both FastISel and GlobalISel can use. llvm-svn: 305672
2017-06-19 17:40:51 +08:00
define arm_aapcscc i32 @test_cmp_i32_eq(i32 %a, i32 %b) {
; CHECK-LABEL: test_cmp_i32_eq:
; CHECK: mov [[V:r[0-9]+]], #0
; CHECK: cmp r0, r1
; CHECK: moveq [[V]], #1
; CHECK: and r0, [[V]], #1
; CHECK: bx lr
entry:
%v = icmp eq i32 %a, %b
%r = zext i1 %v to i32
ret i32 %r
}
define arm_aapcscc i32 @test_cmp_ptr_neq(double *%a, double *%b) {
; CHECK-LABEL: test_cmp_ptr_neq:
; CHECK: mov [[V:r[0-9]+]], #0
; CHECK: cmp r0, r1
; CHECK: movne [[V]], #1
; CHECK: and r0, [[V]], #1
; CHECK: bx lr
entry:
%v = icmp ne double * %a, %b
%r = zext i1 %v to i32
ret i32 %r
}
[ARM] GlobalISel: Support G_ICMP for s8 and s16 Widen to s32 (like all other binary ops). llvm-svn: 305683
2017-06-19 19:47:28 +08:00
define arm_aapcscc i32 @test_cmp_i16_slt(i16 %a, i16 %b) {
; CHECK-LABEL: test_cmp_i16_slt:
; CHECK-DAG: mov [[V:r[0-9]+]], #0
; CHECK: cmp r0, r1
; CHECK: movlt [[V]], #1
; CHECK: and r0, [[V]], #1
; CHECK: bx lr
entry:
%v = icmp slt i16 %a, %b
%r = zext i1 %v to i32
ret i32 %r
}
[ARM] GlobalISel: Support G_SELECT for i32 * Mark as legal for (s32, i1, s32, s32) * Map everything into GPRs * Select to two instructions: a CMP of the condition against 0, to set the flags, and a MOVCCr to select between the two inputs based on the flags that we've just set llvm-svn: 306382
2017-06-27 17:19:51 +08:00
define arm_aapcscc i32 @test_select_i32(i32 %a, i32 %b, i1 %cond) {
; CHECK-LABEL: test_select_i32
; CHECK: cmp r2, #0
; CHECK: moveq r0, r1
; CHECK: bx lr
entry:
%r = select i1 %cond, i32 %a, i32 %b
ret i32 %r
}
[ARM] GlobalISel: Support G_SELECT for pointers All we need to do is mark it as legal, otherwise it's just like s32. llvm-svn: 306390
2017-06-27 18:29:50 +08:00
define arm_aapcscc i32* @test_select_ptr(i32* %a, i32* %b, i1 %cond) {
; CHECK-LABEL: test_select_ptr
; CHECK: cmp r2, #0
; CHECK: moveq r0, r1
; CHECK: bx lr
entry:
%r = select i1 %cond, i32* %a, i32* %b
ret i32* %r
}
[ARM] GlobalISel: Support G_BR This boils down to not crashing in reg bank select due to the lack of register operands on this instruction, and adding some tests. The instruction selection is already covered by the TableGen'erated code. llvm-svn: 307904
2017-07-13 19:09:34 +08:00
define arm_aapcscc void @test_br() {
; CHECK-LABEL: test_br
; CHECK: [[LABEL:.L[[:alnum:]_]+]]:
; CHECK: b [[LABEL]]
entry:
br label %infinite
infinite:
br label %infinite
}
[ARM] GlobalISel: Support G_BRCOND Insert a TSTri to set the flags and a Bcc to branch based on their values. This is a bit inefficient in the (common) cases where the condition for the branch comes from a compare right before the branch, since we set the flags both as part of the compare lowering and as part of the branch lowering. We're going to live with that until we settle on a principled way to handle this kind of situation, which occurs with other patterns as well (combines might be the way forward here). llvm-svn: 308009
2017-07-14 17:46:06 +08:00
declare arm_aapcscc void @brcond1()
declare arm_aapcscc void @brcond2()
define arm_aapcscc void @test_brcond(i32 %n) {
; CHECK-LABEL: test_brcond
; CHECK: cmp r0
; CHECK-NEXT: movgt [[RCMP:r[0-9]+]], #1
; CHECK: tst [[RCMP]], #1
[ARM GlobalISel] Fix selecting G_BRCOND When lowering a G_BRCOND, we generate a TSTri of the condition against 1, which sets the flags, and then a Bcc which branches based on the value of the flags. Unfortunately, we were using the wrong condition code to check whether we need to branch (EQ instead of NE), which caused all our branches to do the opposite of what they were intended to do. This patch fixes the issue by using the correct condition code. llvm-svn: 319313
2017-11-29 22:20:06 +08:00
; CHECK-NEXT: beq [[FALSE:.L[[:alnum:]_]+]]
[ARM GlobalISel] Fix call opcodes We were generating BLX for all the calls, which was incorrect in most cases. Update ARMCallLowering to generate BL for direct calls, and BLX, BX_CALL or BMOVPCRX_CALL for indirect calls. llvm-svn: 316570
2017-10-25 19:42:40 +08:00
; CHECK: bl brcond1
[ARM] GlobalISel: Support G_BRCOND Insert a TSTri to set the flags and a Bcc to branch based on their values. This is a bit inefficient in the (common) cases where the condition for the branch comes from a compare right before the branch, since we set the flags both as part of the compare lowering and as part of the branch lowering. We're going to live with that until we settle on a principled way to handle this kind of situation, which occurs with other patterns as well (combines might be the way forward here). llvm-svn: 308009
2017-07-14 17:46:06 +08:00
; CHECK: [[FALSE]]:
[ARM GlobalISel] Fix call opcodes We were generating BLX for all the calls, which was incorrect in most cases. Update ARMCallLowering to generate BL for direct calls, and BLX, BX_CALL or BMOVPCRX_CALL for indirect calls. llvm-svn: 316570
2017-10-25 19:42:40 +08:00
; CHECK: bl brcond2
[ARM] GlobalISel: Support G_BRCOND Insert a TSTri to set the flags and a Bcc to branch based on their values. This is a bit inefficient in the (common) cases where the condition for the branch comes from a compare right before the branch, since we set the flags both as part of the compare lowering and as part of the branch lowering. We're going to live with that until we settle on a principled way to handle this kind of situation, which occurs with other patterns as well (combines might be the way forward here). llvm-svn: 308009
2017-07-14 17:46:06 +08:00
entry:
%cmp = icmp sgt i32 %n, 0
br i1 %cmp, label %if.true, label %if.false
if.true:
call arm_aapcscc void @brcond1()
br label %if.end
if.false:
call arm_aapcscc void @brcond2()
br label %if.end
if.end:
ret void
}