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llvm-project/llvm/test/CodeGen/WebAssembly/i32.ll

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WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
; RUN: llc < %s -asm-verbose=false | FileCheck %s
WebAssembly: handle more than int32 argument/return Summary: Also test 64-bit integers, except shifts for now which are broken because isel dislikes the 32-bit truncate that precedes them. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11699 llvm-svn: 243822
2015-08-01 12:48:44 +08:00
; Test that basic 32-bit integer operations assemble as expected.
[WebAssembly] Use the default alignment for SIMD types. Previously WebAssembly's datalayout string had -v128:8:128. This had been an attempt to declare a certain level of support for unaligned SIMD accesses. However, clang makes its own determinations for SIMD alignment that are independent of the datalayout string, so this wasn't actually meaningful. llvm-svn: 245494
2015-08-20 04:30:20 +08:00
target datalayout = "e-p:32:32-i64:64-n32:64-S128"
WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
target triple = "wasm32-unknown-unknown"
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
declare i32 @llvm.ctlz.i32(i32, i1)
declare i32 @llvm.cttz.i32(i32, i1)
declare i32 @llvm.ctpop.i32(i32)
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: add32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.add $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
define i32 @add32(i32 %x, i32 %y) {
%a = add i32 %x, %y
ret i32 %a
}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sub32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.sub $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @sub32(i32 %x, i32 %y) {
%a = sub i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: mul32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.mul $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @mul32(i32 %x, i32 %y) {
%a = mul i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sdiv32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.div_s $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @sdiv32(i32 %x, i32 %y) {
%a = sdiv i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: udiv32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.div_u $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @udiv32(i32 %x, i32 %y) {
%a = udiv i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: srem32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.rem_s $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @srem32(i32 %x, i32 %y) {
%a = srem i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: urem32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.rem_u $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @urem32(i32 %x, i32 %y) {
%a = urem i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: and32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.and $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @and32(i32 %x, i32 %y) {
%a = and i32 %x, %y
ret i32 %a
}
[WebAssembly] Rename ior operator to or to match the spec Summary: The spec uses "or" for inclusive-or and "xor" for exclusive-or Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14362 llvm-svn: 252174
2015-11-06 01:08:11 +08:00
; CHECK-LABEL: or32:
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.or $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Rename ior operator to or to match the spec Summary: The spec uses "or" for inclusive-or and "xor" for exclusive-or Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14362 llvm-svn: 252174
2015-11-06 01:08:11 +08:00
define i32 @or32(i32 %x, i32 %y) {
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
%a = or i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: xor32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.xor $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @xor32(i32 %x, i32 %y) {
%a = xor i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: shl32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.shl $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @shl32(i32 %x, i32 %y) {
%a = shl i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: shr32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.shr_u $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @shr32(i32 %x, i32 %y) {
%a = lshr i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: sar32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.shr_s $push0, $0, $1{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @sar32(i32 %x, i32 %y) {
%a = ashr i32 %x, %y
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: clz32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.clz $push0, $0{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @clz32(i32 %x) {
%a = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: clz32_zero_undef:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.clz $push0, $0{{$}}
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Implement the is_zero_undef forms of cttz and ctlz llvm-svn: 245851
2015-08-25 00:39:37 +08:00
define i32 @clz32_zero_undef(i32 %x) {
%a = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: ctz32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.ctz $push0, $0{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @ctz32(i32 %x) {
%a = call i32 @llvm.cttz.i32(i32 %x, i1 false)
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: ctz32_zero_undef:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.ctz $push0, $0{{$}}
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Implement the is_zero_undef forms of cttz and ctlz llvm-svn: 245851
2015-08-25 00:39:37 +08:00
define i32 @ctz32_zero_undef(i32 %x) {
%a = call i32 @llvm.cttz.i32(i32 %x, i1 true)
ret i32 %a
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 08:27:55 +08:00
; CHECK-LABEL: popcnt32:
; CHECK-NEXT: .param i32{{$}}
; CHECK-NEXT: .result i32{{$}}
[WebAssembly] Enable register coloring and register stackifying. This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
2015-11-19 00:12:01 +08:00
; CHECK-NEXT: i32.popcnt $push0, $0{{$}}
; CHECK-NEXT: return $pop0{{$}}
WebAssembly: print basic integer assembly. Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
2015-08-01 01:53:38 +08:00
define i32 @popcnt32(i32 %x) {
%a = call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %a
}