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llvm-project/llvm/test/MC/X86/intel-syntax-unsized-memory.s

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[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80. The X86AsmParser intel handling was refactored in r216481, making it try each different memory operand size to see which one matches. Operand sizes larger than 80 ("[xyz]mmword ptr") were forgotten, which led to an "invalid operand" error for code such as: movdqa [rax], xmm0 llvm-svn: 223187
2014-12-03 10:03:26 +08:00
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -mcpu=knl %s | FileCheck %s
// Check that we deduce unsized memory operands in the general, unambiguous, case.
// We can't deduce xword memory operands, because there is no instruction
// unambiguously accessing 80-bit memory.
// CHECK: movb %al, (%rax)
mov [rax], al
// CHECK: movw %ax, (%rax)
mov [rax], ax
// CHECK: movl %eax, (%rax)
mov [rax], eax
// CHECK: movq %rax, (%rax)
mov [rax], rax
// CHECK: movdqa %xmm0, (%rax)
movdqa [rax], xmm0
// CHECK: vmovdqa %ymm0, (%rax)
vmovdqa [rax], ymm0
// CHECK: vaddps (%rax), %zmm1, %zmm1
vaddps zmm1, zmm1, [rax]
[MC] Reset the MCInst in the matcher function before adding opcode/operands. On X86, the Intel asm parser tries to match all memory operand sizes when none is explicitly specified. For LEA, which doesn't really have a memory operand (just a pointer one), this results in multiple successful matches, one for each memory size. There's no error because it's same opcode, so really, it's just one match. However, the tablegen'd matcher function adds opcode/operands to the passed MCInst, and this results in multiple duplicated operands. This commit clears the MCInst in the tablegen'd matcher function. We sometimes clear it when the match failed, so there's no expectation of keeping the previous content anyway. Differential Revision: http://reviews.llvm.org/D6670 llvm-svn: 224347
2014-12-17 02:05:28 +08:00
// CHECK: leal 1(%r15d), %r9d
lea r9d, [r15d+1]