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llvm-project/llvm/lib/Target/Mips/CMakeLists.txt

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llvmbuildectomy - replace llvm-build by plain cmake No longer rely on an external tool to build the llvm component layout. Instead, leverage the existing `add_llvm_componentlibrary` cmake function and introduce `add_llvm_component_group` to accurately describe component behavior. These function store extra properties in the created targets. These properties are processed once all components are defined to resolve library dependencies and produce the header expected by llvm-config. Differential Revision: https://reviews.llvm.org/D90848
2020-10-10 00:41:21 +08:00
add_llvm_component_group(Mips HAS_JIT)
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
set(LLVM_TARGET_DEFINITIONS Mips.td)
Sort targetgen calls in lib/Target/*/CMakeLists. Makes it easier to see mistakes such as the one fixed in r329178 and makes the different target CMakeLists more consistent. Also remove some stale-looking comments from the Nios2 target cmakefile. No intended behavior change. llvm-svn: 329181
2018-04-04 20:37:44 +08:00
tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just added a layer of indirection with no value (not even conciseness). llvm-svn: 143727
2011-11-05 03:04:23 +08:00
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
Sort targetgen calls in lib/Target/*/CMakeLists. Makes it easier to see mistakes such as the one fixed in r329178 and makes the different target CMakeLists more consistent. Also remove some stale-looking comments from the Nios2 target cmakefile. No intended behavior change. llvm-svn: 329181
2018-04-04 20:37:44 +08:00
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just added a layer of indirection with no value (not even conciseness). llvm-svn: 143727
2011-11-05 03:04:23 +08:00
tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
Sort targetgen calls in lib/Target/*/CMakeLists. Makes it easier to see mistakes such as the one fixed in r329178 and makes the different target CMakeLists more consistent. Also remove some stale-looking comments from the Nios2 target cmakefile. No intended behavior change. llvm-svn: 329181
2018-04-04 20:37:44 +08:00
tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
enable fast isel tablegen files for Mips Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3498 llvm-svn: 207256
2014-04-26 02:36:38 +08:00
tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
[MIPS GlobalISel] Select add i32, i32 Add the minimal support necessary to lower a function that returns the sum of two i32 values. Support argument/return lowering of i32 values through registers only. Add tablegen for regbankselect and instructionselect. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D44304 llvm-svn: 329819
2018-04-11 23:12:32 +08:00
tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
Sort targetgen calls in lib/Target/*/CMakeLists. Makes it easier to see mistakes such as the one fixed in r329178 and makes the different target CMakeLists more consistent. Also remove some stale-looking comments from the Nios2 target cmakefile. No intended behavior change. llvm-svn: 329181
2018-04-04 20:37:44 +08:00
tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
MIPS DSP: add code necessary for pseudo instruction lowering. llvm-svn: 164747
2012-09-27 09:59:07 +08:00
tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
[MIPS GlobalISel] Select add i32, i32 Add the minimal support necessary to lower a function that returns the sum of two i32 values. Support argument/return lowering of i32 values through registers only. Add tablegen for regbankselect and instructionselect. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D44304 llvm-svn: 329819
2018-04-11 23:12:32 +08:00
tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
Sort targetgen calls in lib/Target/*/CMakeLists. Makes it easier to see mistakes such as the one fixed in r329178 and makes the different target CMakeLists more consistent. Also remove some stale-looking comments from the Nios2 target cmakefile. No intended behavior change. llvm-svn: 329181
2018-04-04 20:37:44 +08:00
tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
[Mips][llvm-exegesis] Add a Mips target The target does just enough to be able to run llvm-exegesis in latency mode for at least some opcodes. Patch by Miloš Stojanović. Differential Revision: https://reviews.llvm.org/D68649 llvm-svn: 374590
2019-10-12 04:26:08 +08:00
tablegen(LLVM MipsGenExegesis.inc -gen-exegesis)
Sort targetgen calls in lib/Target/*/CMakeLists. Makes it easier to see mistakes such as the one fixed in r329178 and makes the different target CMakeLists more consistent. Also remove some stale-looking comments from the Nios2 target cmakefile. No intended behavior change. llvm-svn: 329181
2018-04-04 20:37:44 +08:00
Clean up a pile of hacks in our CMake build relating to TableGen. The first problem to fix is to stop creating synthetic *Table_gen targets next to all of the LLVM libraries. These had no real effect as CMake specifies that add_custom_command(OUTPUT ...) directives (what the 'tablegen(...)' stuff expands to) are implicitly added as dependencies to all the rules in that CMakeLists.txt. These synthetic rules started to cause problems as we started more and more heavily using tablegen files from *subdirectories* of the one where they were generated. Within those directories, the set of tablegen outputs was still available and so these synthetic rules added them as dependencies of those subdirectories. However, they were no longer properly associated with the custom command to generate them. Most of the time this "just worked" because something would get to the parent directory first, and run tablegen there. Once run, the files existed and the build proceeded happily. However, as more and more subdirectories have started using this, the probability of this failing to happen has increased. Recently with the MC refactorings, it became quite common for me when touching a large enough number of targets. To add insult to injury, several of the backends *tried* to fix this by adding explicit dependencies back to the parent directory's tablegen rules, but those dependencies didn't work as expected -- they weren't forming a linear chain, they were adding another thread in the race. This patch removes these synthetic rules completely, and adds a much simpler function to declare explicitly that a collection of tablegen'ed files are referenced by other libraries. From that, we can add explicit dependencies from the smaller libraries (such as every architectures Desc library) on this and correctly form a linear sequence. All of the backends are updated to use it, sometimes replacing the existing attempt at adding a dependency, sometimes adding a previously missing dependency edge. Please let me know if this causes any problems, but it fixes a rather persistent and problematic source of build flakiness on our end. llvm-svn: 136023
2011-07-26 08:09:08 +08:00
add_public_tablegen_target(MipsCommonTableGen)
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
Separate MIPS asmprinter llvm-svn: 68383
2009-04-03 18:41:41 +08:00
add_llvm_target(MipsCodeGen
Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering and MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. llvm-svn: 161090
2012-08-01 06:50:19 +08:00
Mips16FrameLowering.cpp
Checkin in of first of several patches to finish implementation of mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
2013-05-11 06:25:39 +08:00
Mips16HardFloat.cpp
This patch has two main functions: 1) Fix a specific bug when certain conversion functions are called in a program compiled as mips16 with hard float and the program is linked as c++. There are two libraries that are reversed in the link order with gcc/g++ and clang/clang++ for mips16 in this case and the proper stubs will then not be called. These stubs are normally handled in the Mips16HardFloat pass but in this case we don't know at that time that we need to generate the stubs. This must all be handled later in code generation and we have moved this functionality to MipsAsmPrinter. When linked as C (gcc or clang) the proper stubs are linked in from libc. 2) Set up the infrastructure to handle 90% of what is in the Mips16HardFloat pass in this new area of MipsAsmPrinter. This is a more logical place to handle this and we have known for some time that we needed to move the code later and not implement it using inline asm as we do now but it was not clear exactly where to do this and what mechanism should be used. Now it's clear to us how to do this and this patch contains the infrastructure to move most of this to MipsAsmPrinter but the actual moving will be done in a follow on patch. The same infrastructure is used to fix this current bug as described in #1. This change was requested by the list during the original putback of the Mips16HardFloat pass but was not practical for us do at that time. llvm-svn: 201426
2014-02-15 03:16:39 +08:00
Mips16HardFloatInfo.cpp
Add Mips16InstrInfo.cpp and MipsSEInstrInfo.cpp to CMakeLists.txt. llvm-svn: 161083
2012-08-01 06:11:05 +08:00
Mips16InstrInfo.cpp
[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for mips16 and MipsSEDAGToDAGISel is for mips32/64. No functionality changes. llvm-svn: 177089
2013-03-15 02:27:31 +08:00
Mips16ISelDAGToDAG.cpp
Add back lines which were accidentally deleted in CMakeLists.txt. llvm-svn: 177096
2013-03-15 02:46:46 +08:00
Mips16ISelLowering.cpp
Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and MipsSERegisterInfo. llvm-svn: 161092
2012-08-01 07:41:32 +08:00
Mips16RegisterInfo.cpp
Target/Mips: Unbreak CMake build. llvm-svn: 148909
2012-01-25 11:15:46 +08:00
MipsAnalyzeImmediate.cpp
move all the target's asmprinters into the main target. The piece that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056
2010-11-15 02:43:56 +08:00
MipsAsmPrinter.cpp
[MIPS GlobalISel] Adding GlobalISel Add GlobalISel infrastructure up to the point where we can select a ret void. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D43583 llvm-svn: 325888
2018-02-23 19:06:40 +08:00
MipsCallLowering.cpp
[mips] Move MipsCCState to a separate file and clang-formatted it. Summary: Depends on D6113 Reviewers: theraven, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6114 llvm-svn: 221525
2014-11-07 22:24:31 +08:00
MipsCCState.cpp
Add the skeleton for the Mips constant island pass. It will only be used for Mips 16 at this time. llvm-svn: 176161
2013-02-27 11:33:58 +08:00
MipsConstantIslandPass.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
MipsDelaySlotFiller.cpp
[mips] Fix atomic operations at O0, v3 Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the stores can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This version addresses issues with the initial implementation and covers all atomic operations. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Patch By: Simon Dardis Differential Revision: https://reviews.llvm.org/D31287 llvm-svn: 336328
2018-07-05 17:27:05 +08:00
MipsExpandPseudo.cpp
Start pushing changes for Mips Fast-Isel llvm-svn: 206505
2014-04-18 06:15:34 +08:00
MipsFastISel.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
MipsInstrInfo.cpp
[MIPS GlobalISel] Adding GlobalISel Add GlobalISel infrastructure up to the point where we can select a ret void. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D43583 llvm-svn: 325888
2018-02-23 19:06:40 +08:00
MipsInstructionSelector.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
MipsISelDAGToDAG.cpp
MipsISelLowering.cpp
Update CMake stuff llvm-svn: 123171
2011-01-10 20:39:23 +08:00
MipsFrameLowering.cpp
[MIPS GlobalISel] Adding GlobalISel Add GlobalISel infrastructure up to the point where we can select a ret void. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D43583 llvm-svn: 325888
2018-02-23 19:06:40 +08:00
MipsLegalizerInfo.cpp
[mips] Merge MipsLongBranch and MipsHazardSchedule passes MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it potentially breaks some jumps, so they have to be expanded to long branches. When some branch is expanded to long branch, it potentially creates a hazard situation, which should be fixed by adding nops. New pass is called MipsBranchExpansion, it combines these two passes, and runs them alternately until one of them reports no changes were made. Differential Revision: https://reviews.llvm.org/D46641 llvm-svn: 332977
2018-05-22 21:24:38 +08:00
MipsBranchExpansion.cpp
Define class MipsMCInstLower. llvm-svn: 134633
2011-07-08 04:24:54 +08:00
MipsMCInstLower.cpp
Fix up the CMake build for the new files added in r146960, they're likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
2011-12-20 16:42:11 +08:00
MipsMachineFunction.cpp
This patch enables llvm to switch between compiling for mips32/mips64 and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. llvm-svn: 179118
2013-04-10 03:46:01 +08:00
MipsModuleISelDAGToDAG.cpp
Add MipsOptimizePICCall.cpp to CMakeLists.txt. llvm-svn: 195894
2013-11-28 07:47:25 +08:00
MipsOptimizePICCall.cpp
This is for an experimental option -mips-os16. The idea is to compile all Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this would happen as long as floating point instructions are not needed. Probably it would also make sense to compile as mips32 if atomic operations are needed too. There may be other cases too. A module pass prescans the IR and adds the mips16 or nomips16 attribute to functions depending on the functions needs. Mips 16 mode can result in a 40% code compression by utililizing 16 bit encoding of many instructions. The hope is for this to replace the traditional gcc way of dealing with Mips16 code using floating point which involves essentially using soft float but with a library implemented using mips32 floating point. This gcc method also requires creating stubs so that Mips32 code can interact with these Mips 16 functions that have floating point needs. My conjecture is that in reality this traditional gcc method would never win over this new method. I will be implementing the traditional gcc method also. Some of it is already done but I needed to do the stubs to finish the work and those required this mips16/32 mixed mode capability. I have more ideas for to make this new method much better and I think the old method will just live in llvm for anyone that needs the backward compatibility but I don't for what reason that would be needed. llvm-svn: 179185
2013-04-11 00:58:04 +08:00
MipsOs16.cpp
[MIPS GlobalISel] Add pre legalizer combiner pass Introduce GlobalISel pre legalizer pass for MIPS. It will be used to cope with instructions that require combining before legalization. Differential Revision: https://reviews.llvm.org/D56269 llvm-svn: 351046
2019-01-14 18:27:05 +08:00
MipsPreLegalizerCombiner.cpp
[MIPS GlobalISel] Adding GlobalISel Add GlobalISel infrastructure up to the point where we can select a ret void. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D43583 llvm-svn: 325888
2018-02-23 19:06:40 +08:00
MipsRegisterBankInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
MipsRegisterInfo.cpp
Add definitions of two subclasses of MipsFrameLowering, Mips16FrameLowering and MipsSEFrameLowering. Implement MipsSEFrameLowering::hasReservedCallFrame. Call frames will not be reserved if there is a call with a large call frame or there are variable sized objects on the stack. llvm-svn: 161090
2012-08-01 06:50:19 +08:00
MipsSEFrameLowering.cpp
Add Mips16InstrInfo.cpp and MipsSEInstrInfo.cpp to CMakeLists.txt. llvm-svn: 161083
2012-08-01 06:11:05 +08:00
MipsSEInstrInfo.cpp
[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for mips16 and MipsSEDAGToDAGISel is for mips32/64. No functionality changes. llvm-svn: 177089
2013-03-15 02:27:31 +08:00
MipsSEISelDAGToDAG.cpp
Add back lines which were accidentally deleted in CMakeLists.txt. llvm-svn: 177096
2013-03-15 02:46:46 +08:00
MipsSEISelLowering.cpp
Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and MipsSERegisterInfo. llvm-svn: 161092
2012-08-01 07:41:32 +08:00
MipsSERegisterInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
MipsSubtarget.cpp
MipsTargetMachine.cpp
reintroduce support for Mips "small" section handling. This is implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. llvm-svn: 78900
2009-08-13 14:28:06 +08:00
MipsTargetObjectFile.cpp
[mips][microMIPS] Adding code size reduction pass for MicroMIPS Author: milena.vujosevic.janicic Reviewers: sdardis The code implements size reduction pass for MicroMIPS. Load and store instructions are examined and transformed, if possible. lw32 instruction is transformed into 16-bit instruction lwsp sw32 instruction is transformed into 16-bit instruction swsp Arithmetic instrcutions are examined and transformed, if possible. addu32 instruction is transformed into 16-bit instruction addu16 subu32 instruction is transformed into 16-bit instruction subu16 Differential Revision: https://reviews.llvm.org/D15144 llvm-svn: 301540
2017-04-27 21:10:48 +08:00
MicroMipsSizeReduction.cpp
llvmbuildectomy - replace llvm-build by plain cmake No longer rely on an external tool to build the llvm component layout. Instead, leverage the existing `add_llvm_componentlibrary` cmake function and introduce `add_llvm_component_group` to accurately describe component behavior. These function store extra properties in the created targets. These properties are processed once all components are defined to resolve library dependencies and produce the header expected by llvm-config. Differential Revision: https://reviews.llvm.org/D90848
2020-10-10 00:41:21 +08:00
LINK_COMPONENTS
Analysis
AsmPrinter
CodeGen
Core
MC
MipsDesc
MipsInfo
SelectionDAG
Support
Target
GlobalISel
ADD_TO_COMPONENT
Mips
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
)
Use explicit add_subdirectory's for LLVM target sublibraries instead of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068
2011-02-20 10:55:27 +08:00
Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt llvm-svn: 330584
2018-04-23 20:49:34 +08:00
add_subdirectory(AsmParser)
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
add_subdirectory(Disassembler)
Next round of MC refactoring. This patch factor MC table instantiations, MC registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
2011-07-15 04:59:42 +08:00
add_subdirectory(MCTargetDesc)
Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt llvm-svn: 330584
2018-04-23 20:49:34 +08:00
add_subdirectory(TargetInfo)