2010-07-20 23:41:07 +08:00
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//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SplitAnalysis class as well as mutator functions for
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// live range splitting.
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//
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//===----------------------------------------------------------------------===//
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2010-11-04 04:39:23 +08:00
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#define DEBUG_TYPE "regalloc"
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2010-07-20 23:41:07 +08:00
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#include "SplitKit.h"
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2010-10-15 07:49:52 +08:00
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#include "LiveRangeEdit.h"
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2010-07-27 07:44:11 +08:00
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#include "VirtRegMap.h"
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2011-03-03 07:05:19 +08:00
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#include "llvm/ADT/Statistic.h"
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2010-08-11 01:07:22 +08:00
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#include "llvm/CodeGen/CalcSpillWeights.h"
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2010-07-20 23:41:07 +08:00
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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2010-10-29 04:34:50 +08:00
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#include "llvm/CodeGen/MachineDominators.h"
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2010-07-27 07:44:11 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2010-07-20 23:41:07 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2010-07-21 05:46:58 +08:00
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#include "llvm/Support/CommandLine.h"
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2010-07-20 23:41:07 +08:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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2010-07-21 05:46:58 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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2010-07-20 23:41:07 +08:00
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using namespace llvm;
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2010-07-21 05:46:58 +08:00
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static cl::opt<bool>
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AllowSplit("spiller-splits-edges",
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cl::desc("Allow critical edge splitting during spilling"));
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2010-07-20 23:41:07 +08:00
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2011-03-03 07:05:19 +08:00
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STATISTIC(NumFinished, "Number of splits finished");
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STATISTIC(NumSimple, "Number of splits that were simple");
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2010-07-20 23:41:07 +08:00
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//===----------------------------------------------------------------------===//
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// Split Analysis
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//===----------------------------------------------------------------------===//
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2011-02-19 08:53:42 +08:00
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SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
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2010-07-21 07:50:15 +08:00
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const LiveIntervals &lis,
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const MachineLoopInfo &mli)
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2011-02-19 08:53:42 +08:00
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: MF(vrm.getMachineFunction()),
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VRM(vrm),
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2011-01-26 08:50:53 +08:00
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LIS(lis),
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Loops(mli),
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2011-02-19 08:53:42 +08:00
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TII(*MF.getTarget().getInstrInfo()),
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2011-01-26 08:50:53 +08:00
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CurLI(0) {}
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2010-07-20 23:41:07 +08:00
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void SplitAnalysis::clear() {
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2011-01-19 05:13:27 +08:00
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UseSlots.clear();
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2011-01-26 08:50:53 +08:00
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UsingInstrs.clear();
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UsingBlocks.clear();
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2011-02-10 06:50:26 +08:00
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LiveBlocks.clear();
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2011-01-26 08:50:53 +08:00
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CurLI = 0;
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2010-07-20 23:41:07 +08:00
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}
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2010-07-21 05:46:58 +08:00
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bool SplitAnalysis::canAnalyzeBranch(const MachineBasicBlock *MBB) {
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MachineBasicBlock *T, *F;
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SmallVector<MachineOperand, 4> Cond;
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2011-01-26 08:50:53 +08:00
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return !TII.AnalyzeBranch(const_cast<MachineBasicBlock&>(*MBB), T, F, Cond);
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2010-07-21 05:46:58 +08:00
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}
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2011-01-26 08:50:53 +08:00
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/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
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2010-07-21 00:12:37 +08:00
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void SplitAnalysis::analyzeUses() {
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2011-01-26 08:50:53 +08:00
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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2011-02-10 05:52:09 +08:00
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for (MachineRegisterInfo::reg_iterator I = MRI.reg_begin(CurLI->reg),
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E = MRI.reg_end(); I != E; ++I) {
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MachineOperand &MO = I.getOperand();
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if (MO.isUse() && MO.isUndef())
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continue;
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MachineInstr *MI = MO.getParent();
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2011-01-26 08:50:53 +08:00
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if (MI->isDebugValue() || !UsingInstrs.insert(MI))
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2010-07-20 23:41:07 +08:00
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continue;
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2011-01-26 08:50:53 +08:00
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UseSlots.push_back(LIS.getInstructionIndex(MI).getDefIndex());
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2010-07-20 23:41:07 +08:00
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MachineBasicBlock *MBB = MI->getParent();
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2011-02-10 07:56:18 +08:00
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UsingBlocks[MBB]++;
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2010-07-20 23:41:07 +08:00
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}
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2011-01-19 05:13:27 +08:00
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array_pod_sort(UseSlots.begin(), UseSlots.end());
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2011-02-10 06:50:26 +08:00
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calcLiveBlockInfo();
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2010-08-13 02:50:55 +08:00
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DEBUG(dbgs() << " counted "
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2011-01-26 08:50:53 +08:00
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<< UsingInstrs.size() << " instrs, "
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2011-02-10 07:56:18 +08:00
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<< UsingBlocks.size() << " blocks.\n");
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2010-07-20 23:41:07 +08:00
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}
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2011-02-10 06:50:26 +08:00
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/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
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/// where CurLI is live.
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void SplitAnalysis::calcLiveBlockInfo() {
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if (CurLI->empty())
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return;
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LiveInterval::const_iterator LVI = CurLI->begin();
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LiveInterval::const_iterator LVE = CurLI->end();
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SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
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UseI = UseSlots.begin();
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UseE = UseSlots.end();
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// Loop over basic blocks where CurLI is live.
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MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
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for (;;) {
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BlockInfo BI;
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BI.MBB = MFI;
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2011-03-03 11:41:29 +08:00
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tie(BI.Start, BI.Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
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2011-02-10 06:50:26 +08:00
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// The last split point is the latest possible insertion point that dominates
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// all successor blocks. If interference reaches LastSplitPoint, it is not
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// possible to insert a split or reload that makes CurLI live in the
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// outgoing bundle.
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MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
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if (LSP == BI.MBB->end())
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2011-03-03 11:41:29 +08:00
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BI.LastSplitPoint = BI.Stop;
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2011-02-10 06:50:26 +08:00
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else
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BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
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// LVI is the first live segment overlapping MBB.
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2011-03-03 11:41:29 +08:00
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BI.LiveIn = LVI->start <= BI.Start;
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2011-02-10 06:50:26 +08:00
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if (!BI.LiveIn)
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BI.Def = LVI->start;
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// Find the first and last uses in the block.
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BI.Uses = hasUses(MFI);
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if (BI.Uses && UseI != UseE) {
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BI.FirstUse = *UseI;
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2011-03-03 11:41:29 +08:00
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assert(BI.FirstUse >= BI.Start);
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2011-02-10 06:50:26 +08:00
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do ++UseI;
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2011-03-03 11:41:29 +08:00
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while (UseI != UseE && *UseI < BI.Stop);
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2011-02-10 06:50:26 +08:00
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BI.LastUse = UseI[-1];
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2011-03-03 11:41:29 +08:00
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assert(BI.LastUse < BI.Stop);
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2011-02-10 06:50:26 +08:00
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}
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// Look for gaps in the live range.
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bool hasGap = false;
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BI.LiveOut = true;
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2011-03-03 11:41:29 +08:00
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while (LVI->end < BI.Stop) {
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2011-02-10 06:50:26 +08:00
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SlotIndex LastStop = LVI->end;
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2011-03-03 11:41:29 +08:00
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if (++LVI == LVE || LVI->start >= BI.Stop) {
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2011-02-10 06:50:26 +08:00
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BI.Kill = LastStop;
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BI.LiveOut = false;
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break;
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}
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if (LastStop < LVI->start) {
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hasGap = true;
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BI.Kill = LastStop;
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BI.Def = LVI->start;
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}
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}
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// Don't set LiveThrough when the block has a gap.
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BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
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LiveBlocks.push_back(BI);
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// LVI is now at LVE or LVI->end >= Stop.
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if (LVI == LVE)
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break;
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// Live segment ends exactly at Stop. Move to the next segment.
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2011-03-03 11:41:29 +08:00
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if (LVI->end == BI.Stop && ++LVI == LVE)
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2011-02-10 06:50:26 +08:00
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break;
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// Pick the next basic block.
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2011-03-03 11:41:29 +08:00
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if (LVI->start < BI.Stop)
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2011-02-10 06:50:26 +08:00
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++MFI;
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else
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MFI = LIS.getMBBFromIndex(LVI->start);
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}
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}
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2011-02-22 07:09:46 +08:00
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bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
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unsigned OrigReg = VRM.getOriginal(CurLI->reg);
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const LiveInterval &Orig = LIS.getInterval(OrigReg);
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assert(!Orig.empty() && "Splitting empty interval?");
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LiveInterval::const_iterator I = Orig.find(Idx);
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// Range containing Idx should begin at Idx.
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if (I != Orig.end() && I->start <= Idx)
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return I->start == Idx;
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// Range does not contain Idx, previous must end at Idx.
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return I != Orig.begin() && (--I)->end == Idx;
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}
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2010-10-23 04:28:21 +08:00
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void SplitAnalysis::print(const BlockPtrSet &B, raw_ostream &OS) const {
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for (BlockPtrSet::const_iterator I = B.begin(), E = B.end(); I != E; ++I) {
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2011-01-26 08:50:53 +08:00
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unsigned count = UsingBlocks.lookup(*I);
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2010-10-23 04:28:21 +08:00
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OS << " BB#" << (*I)->getNumber();
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if (count)
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OS << '(' << count << ')';
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}
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}
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2010-07-20 23:41:07 +08:00
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void SplitAnalysis::analyze(const LiveInterval *li) {
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clear();
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2011-01-26 08:50:53 +08:00
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CurLI = li;
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2010-07-21 00:12:37 +08:00
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analyzeUses();
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2010-07-20 23:41:07 +08:00
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}
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2010-12-16 01:49:52 +08:00
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2010-08-19 03:00:08 +08:00
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//===----------------------------------------------------------------------===//
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2011-03-02 09:59:34 +08:00
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// Split Editor
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2010-08-19 03:00:08 +08:00
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//===----------------------------------------------------------------------===//
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2011-03-02 09:59:34 +08:00
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/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
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SplitEditor::SplitEditor(SplitAnalysis &sa,
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LiveIntervals &lis,
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VirtRegMap &vrm,
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2011-03-03 09:29:13 +08:00
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MachineDominatorTree &mdt)
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2011-03-02 09:59:34 +08:00
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: SA(sa), LIS(lis), VRM(vrm),
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MRI(vrm.getMachineFunction().getRegInfo()),
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MDT(mdt),
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TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
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TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
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2011-03-03 09:29:13 +08:00
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Edit(0),
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2011-03-02 09:59:34 +08:00
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OpenIdx(0),
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RegAssign(Allocator)
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2011-03-03 09:29:13 +08:00
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{}
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void SplitEditor::reset(LiveRangeEdit &lre) {
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Edit = &lre;
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OpenIdx = 0;
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RegAssign.clear();
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Values.clear();
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2011-03-04 08:15:36 +08:00
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// We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
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LiveOutSeen.clear();
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2011-03-03 09:29:13 +08:00
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2011-03-02 09:59:34 +08:00
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// We don't need an AliasAnalysis since we will only be performing
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// cheap-as-a-copy remats anyway.
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2011-03-03 07:31:50 +08:00
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Edit->anyRematerializable(LIS, TII, 0);
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2011-03-02 09:59:34 +08:00
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}
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void SplitEditor::dump() const {
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if (RegAssign.empty()) {
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dbgs() << " empty\n";
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return;
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}
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for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
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dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
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dbgs() << '\n';
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2010-09-14 05:29:45 +08:00
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}
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2011-03-02 09:59:34 +08:00
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VNInfo *SplitEditor::defValue(unsigned RegIdx,
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const VNInfo *ParentVNI,
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SlotIndex Idx) {
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assert(ParentVNI && "Mapping NULL value");
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assert(Idx.isValid() && "Invalid SlotIndex");
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2011-03-03 07:31:50 +08:00
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assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
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LiveInterval *LI = Edit->get(RegIdx);
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2011-03-02 09:59:34 +08:00
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// Create a new value.
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VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
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// Preserve the PHIDef bit.
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if (ParentVNI->isPHIDef() && Idx == ParentVNI->def)
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VNI->setIsPHIDef(true);
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// Use insert for lookup, so we can add missing values with a second lookup.
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std::pair<ValueMap::iterator, bool> InsP =
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Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
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// This was the first time (RegIdx, ParentVNI) was mapped.
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// Keep it as a simple def without any liveness.
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if (InsP.second)
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return VNI;
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// If the previous value was a simple mapping, add liveness for it now.
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if (VNInfo *OldVNI = InsP.first->second) {
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SlotIndex Def = OldVNI->def;
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LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
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// No longer a simple mapping.
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InsP.first->second = 0;
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}
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// This is a complex mapping, add liveness for VNI
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SlotIndex Def = VNI->def;
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LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
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return VNI;
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2010-09-14 07:29:09 +08:00
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}
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2011-03-02 09:59:34 +08:00
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void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
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assert(ParentVNI && "Mapping NULL value");
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VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
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// ParentVNI was either unmapped or already complex mapped. Either way.
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if (!VNI)
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return;
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// This was previously a single mapping. Make sure the old def is represented
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// by a trivial live range.
|
|
|
|
SlotIndex Def = VNI->def;
|
2011-03-03 07:31:50 +08:00
|
|
|
Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
|
2011-03-02 09:59:34 +08:00
|
|
|
VNI = 0;
|
|
|
|
}
|
2010-09-22 06:32:21 +08:00
|
|
|
|
2011-03-02 08:49:28 +08:00
|
|
|
// extendRange - Extend the live range to reach Idx.
|
2010-08-19 03:00:08 +08:00
|
|
|
// Potentially create phi-def values.
|
2011-03-02 09:59:34 +08:00
|
|
|
void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
|
2010-08-19 03:00:08 +08:00
|
|
|
assert(Idx.isValid() && "Invalid SlotIndex");
|
2011-01-26 08:50:53 +08:00
|
|
|
MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
|
2010-08-19 03:00:08 +08:00
|
|
|
assert(IdxMBB && "No MBB at Idx");
|
2011-03-03 07:31:50 +08:00
|
|
|
LiveInterval *LI = Edit->get(RegIdx);
|
2010-08-19 03:00:08 +08:00
|
|
|
|
|
|
|
// Is there a def in the same MBB we can extend?
|
2011-03-02 08:49:28 +08:00
|
|
|
if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
|
|
|
|
return;
|
2010-08-19 03:00:08 +08:00
|
|
|
|
|
|
|
// Now for the fun part. We know that ParentVNI potentially has multiple defs,
|
|
|
|
// and we may need to create even more phi-defs to preserve VNInfo SSA form.
|
2010-10-29 04:34:52 +08:00
|
|
|
// Perform a search for all predecessor blocks where we know the dominating
|
|
|
|
// VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
|
|
|
|
|
2011-03-04 08:15:36 +08:00
|
|
|
// Initialize the live-out cache the first time it is needed.
|
|
|
|
if (LiveOutSeen.empty()) {
|
|
|
|
unsigned N = VRM.getMachineFunction().getNumBlockIDs();
|
|
|
|
LiveOutSeen.resize(N);
|
|
|
|
LiveOutCache.resize(N);
|
|
|
|
}
|
|
|
|
|
2011-01-26 08:50:53 +08:00
|
|
|
// Blocks where LI should be live-in.
|
2010-10-29 04:34:52 +08:00
|
|
|
SmallVector<MachineDomTreeNode*, 16> LiveIn;
|
2011-01-26 08:50:53 +08:00
|
|
|
LiveIn.push_back(MDT[IdxMBB]);
|
2010-10-29 04:34:52 +08:00
|
|
|
|
2011-03-03 09:29:10 +08:00
|
|
|
// Remember if we have seen more than one value.
|
|
|
|
bool UniqueVNI = true;
|
|
|
|
VNInfo *IdxVNI = 0;
|
|
|
|
|
2011-01-26 08:50:53 +08:00
|
|
|
// Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
|
2010-10-29 04:34:52 +08:00
|
|
|
for (unsigned i = 0; i != LiveIn.size(); ++i) {
|
|
|
|
MachineBasicBlock *MBB = LiveIn[i]->getBlock();
|
|
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
|
|
MachineBasicBlock *Pred = *PI;
|
2011-03-04 08:15:36 +08:00
|
|
|
LiveOutPair &LOP = LiveOutCache[Pred];
|
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
// Is this a known live-out block?
|
2011-03-04 08:15:36 +08:00
|
|
|
if (LiveOutSeen.test(Pred->getNumber())) {
|
|
|
|
if (VNInfo *VNI = LOP.first) {
|
2011-03-03 09:29:10 +08:00
|
|
|
if (IdxVNI && IdxVNI != VNI)
|
|
|
|
UniqueVNI = false;
|
|
|
|
IdxVNI = VNI;
|
|
|
|
}
|
2010-10-29 04:34:52 +08:00
|
|
|
continue;
|
2011-03-03 09:29:10 +08:00
|
|
|
}
|
2011-03-04 08:15:36 +08:00
|
|
|
|
|
|
|
// First time. LOP is garbage and must be cleared below.
|
|
|
|
LiveOutSeen.set(Pred->getNumber());
|
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
// Does Pred provide a live-out value?
|
2011-03-02 08:06:15 +08:00
|
|
|
SlotIndex Start, Last;
|
|
|
|
tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
|
|
|
|
Last = Last.getPrevSlot();
|
2011-03-04 08:15:36 +08:00
|
|
|
VNInfo *VNI = LI->extendInBlock(Start, Last);
|
|
|
|
LOP.first = VNI;
|
|
|
|
if (VNI) {
|
|
|
|
LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
|
2011-03-03 09:29:10 +08:00
|
|
|
if (IdxVNI && IdxVNI != VNI)
|
|
|
|
UniqueVNI = false;
|
|
|
|
IdxVNI = VNI;
|
2010-10-29 04:34:52 +08:00
|
|
|
continue;
|
|
|
|
}
|
2011-03-04 08:15:36 +08:00
|
|
|
LOP.second = 0;
|
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
// No, we need a live-in value for Pred as well
|
|
|
|
if (Pred != IdxMBB)
|
2011-01-26 08:50:53 +08:00
|
|
|
LiveIn.push_back(MDT[Pred]);
|
2011-03-03 09:29:10 +08:00
|
|
|
else
|
|
|
|
UniqueVNI = false; // Loopback to IdxMBB, ask updateSSA() for help.
|
2010-08-19 03:00:08 +08:00
|
|
|
}
|
2010-10-29 04:34:52 +08:00
|
|
|
}
|
2010-08-19 03:00:08 +08:00
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
// We may need to add phi-def values to preserve the SSA form.
|
2011-03-03 09:29:10 +08:00
|
|
|
if (UniqueVNI) {
|
|
|
|
LiveOutPair LOP(IdxVNI, MDT[LIS.getMBBFromIndex(IdxVNI->def)]);
|
|
|
|
// Update LiveOutCache, but skip IdxMBB at LiveIn[0].
|
|
|
|
for (unsigned i = 1, e = LiveIn.size(); i != e; ++i)
|
|
|
|
LiveOutCache[LiveIn[i]->getBlock()] = LOP;
|
|
|
|
} else
|
|
|
|
IdxVNI = updateSSA(RegIdx, LiveIn, Idx, IdxMBB);
|
2011-03-02 09:59:34 +08:00
|
|
|
|
|
|
|
// Since we went through the trouble of a full BFS visiting all reaching defs,
|
|
|
|
// the values in LiveIn are now accurate. No more phi-defs are needed
|
|
|
|
// for these blocks, so we can color the live ranges.
|
|
|
|
for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *MBB = LiveIn[i]->getBlock();
|
|
|
|
SlotIndex Start = LIS.getMBBStartIdx(MBB);
|
2011-03-04 08:15:36 +08:00
|
|
|
VNInfo *VNI = LiveOutCache[MBB].first;
|
2011-03-02 09:59:34 +08:00
|
|
|
|
|
|
|
// Anything in LiveIn other than IdxMBB is live-through.
|
|
|
|
// In IdxMBB, we should stop at Idx unless the same value is live-out.
|
|
|
|
if (MBB == IdxMBB && IdxVNI != VNI)
|
|
|
|
LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
|
|
|
|
else
|
|
|
|
LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
|
|
|
|
SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
|
|
|
|
SlotIndex Idx,
|
|
|
|
const MachineBasicBlock *IdxMBB) {
|
2010-10-29 04:34:52 +08:00
|
|
|
// This is essentially the same iterative algorithm that SSAUpdater uses,
|
|
|
|
// except we already have a dominator tree, so we don't have to recompute it.
|
2011-03-03 07:31:50 +08:00
|
|
|
LiveInterval *LI = Edit->get(RegIdx);
|
2010-10-29 04:34:52 +08:00
|
|
|
VNInfo *IdxVNI = 0;
|
|
|
|
unsigned Changes;
|
|
|
|
do {
|
|
|
|
Changes = 0;
|
2011-03-02 09:59:34 +08:00
|
|
|
// Propagate live-out values down the dominator tree, inserting phi-defs
|
|
|
|
// when necessary. Since LiveIn was created by a BFS, going backwards makes
|
|
|
|
// it more likely for us to visit immediate dominators before their
|
|
|
|
// children.
|
2010-10-29 04:34:52 +08:00
|
|
|
for (unsigned i = LiveIn.size(); i; --i) {
|
|
|
|
MachineDomTreeNode *Node = LiveIn[i-1];
|
|
|
|
MachineBasicBlock *MBB = Node->getBlock();
|
|
|
|
MachineDomTreeNode *IDom = Node->getIDom();
|
|
|
|
LiveOutPair IDomValue;
|
2011-03-04 08:15:36 +08:00
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
// We need a live-in value to a block with no immediate dominator?
|
|
|
|
// This is probably an unreachable block that has survived somehow.
|
2011-03-04 08:15:36 +08:00
|
|
|
bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
|
2010-08-19 04:29:53 +08:00
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
// IDom dominates all of our predecessors, but it may not be the immediate
|
|
|
|
// dominator. Check if any of them have live-out values that are properly
|
|
|
|
// dominated by IDom. If so, we need a phi-def here.
|
|
|
|
if (!needPHI) {
|
2011-03-04 08:15:36 +08:00
|
|
|
IDomValue = LiveOutCache[IDom->getBlock()];
|
2010-10-29 04:34:52 +08:00
|
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
2011-01-26 08:50:53 +08:00
|
|
|
LiveOutPair Value = LiveOutCache[*PI];
|
2010-10-29 04:34:52 +08:00
|
|
|
if (!Value.first || Value.first == IDomValue.first)
|
|
|
|
continue;
|
|
|
|
// This predecessor is carrying something other than IDomValue.
|
|
|
|
// It could be because IDomValue hasn't propagated yet, or it could be
|
|
|
|
// because MBB is in the dominance frontier of that value.
|
2011-01-26 08:50:53 +08:00
|
|
|
if (MDT.dominates(IDom, Value.second)) {
|
2010-10-29 04:34:52 +08:00
|
|
|
needPHI = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-08-19 04:29:53 +08:00
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
// Create a phi-def if required.
|
|
|
|
if (needPHI) {
|
|
|
|
++Changes;
|
2011-01-26 08:50:53 +08:00
|
|
|
SlotIndex Start = LIS.getMBBStartIdx(MBB);
|
|
|
|
VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
|
2010-10-29 04:34:52 +08:00
|
|
|
VNI->setIsPHIDef(true);
|
2011-01-26 08:50:53 +08:00
|
|
|
// We no longer need LI to be live-in.
|
2010-10-29 04:34:52 +08:00
|
|
|
LiveIn.erase(LiveIn.begin()+(i-1));
|
|
|
|
// Blocks in LiveIn are either IdxMBB, or have a value live-through.
|
|
|
|
if (MBB == IdxMBB)
|
|
|
|
IdxVNI = VNI;
|
|
|
|
// Check if we need to update live-out info.
|
2011-03-04 08:15:36 +08:00
|
|
|
LiveOutPair &LOP = LiveOutCache[MBB];
|
|
|
|
if (LOP.second == Node || !LiveOutSeen.test(MBB->getNumber())) {
|
2010-10-29 04:34:52 +08:00
|
|
|
// We already have a live-out defined in MBB, so this must be IdxMBB.
|
|
|
|
assert(MBB == IdxMBB && "Adding phi-def to known live-out");
|
2011-01-26 08:50:53 +08:00
|
|
|
LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
|
2010-10-29 04:34:52 +08:00
|
|
|
} else {
|
|
|
|
// This phi-def is also live-out, so color the whole block.
|
2011-01-26 08:50:53 +08:00
|
|
|
LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
|
2011-03-04 08:15:36 +08:00
|
|
|
LOP = LiveOutPair(VNI, Node);
|
2010-10-29 04:34:52 +08:00
|
|
|
}
|
|
|
|
} else if (IDomValue.first) {
|
2010-10-30 01:37:25 +08:00
|
|
|
// No phi-def here. Remember incoming value for IdxMBB.
|
2011-03-04 08:15:36 +08:00
|
|
|
if (MBB == IdxMBB) {
|
2010-10-29 04:34:52 +08:00
|
|
|
IdxVNI = IDomValue.first;
|
2011-03-04 08:15:36 +08:00
|
|
|
// IdxMBB need not be live-out.
|
|
|
|
if (!LiveOutSeen.test(MBB->getNumber()))
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
assert(LiveOutSeen.test(MBB->getNumber()) && "Expected live-out block");
|
2010-10-30 01:37:25 +08:00
|
|
|
// Propagate IDomValue if needed:
|
|
|
|
// MBB is live-out and doesn't define its own value.
|
2011-03-04 08:15:36 +08:00
|
|
|
LiveOutPair &LOP = LiveOutCache[MBB];
|
|
|
|
if (LOP.second != Node && LOP.first != IDomValue.first) {
|
2010-10-29 04:34:52 +08:00
|
|
|
++Changes;
|
2011-03-04 08:15:36 +08:00
|
|
|
LOP = IDomValue;
|
2010-10-29 04:34:52 +08:00
|
|
|
}
|
2010-08-19 04:29:53 +08:00
|
|
|
}
|
2010-08-19 03:00:08 +08:00
|
|
|
}
|
2010-10-29 04:34:52 +08:00
|
|
|
} while (Changes);
|
2010-08-19 03:00:08 +08:00
|
|
|
|
2010-10-29 04:34:52 +08:00
|
|
|
assert(IdxVNI && "Didn't find value for Idx");
|
2011-03-02 09:59:34 +08:00
|
|
|
return IdxVNI;
|
2011-03-02 07:14:53 +08:00
|
|
|
}
|
|
|
|
|
2011-02-03 14:18:29 +08:00
|
|
|
VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
|
2010-11-11 03:31:50 +08:00
|
|
|
VNInfo *ParentVNI,
|
|
|
|
SlotIndex UseIdx,
|
|
|
|
MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) {
|
|
|
|
MachineInstr *CopyMI = 0;
|
|
|
|
SlotIndex Def;
|
2011-03-03 07:31:50 +08:00
|
|
|
LiveInterval *LI = Edit->get(RegIdx);
|
2010-11-11 03:31:50 +08:00
|
|
|
|
|
|
|
// Attempt cheap-as-a-copy rematerialization.
|
|
|
|
LiveRangeEdit::Remat RM(ParentVNI);
|
2011-03-03 07:31:50 +08:00
|
|
|
if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
|
|
|
|
Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
|
2010-11-11 03:31:50 +08:00
|
|
|
} else {
|
|
|
|
// Can't remat, just insert a copy from parent.
|
2011-02-03 14:18:29 +08:00
|
|
|
CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
|
2011-03-03 07:31:50 +08:00
|
|
|
.addReg(Edit->getReg());
|
2011-01-26 08:50:53 +08:00
|
|
|
Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
|
2010-11-11 03:31:50 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Define the value in Reg.
|
2011-03-02 07:14:53 +08:00
|
|
|
VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
|
2010-11-11 03:31:50 +08:00
|
|
|
VNI->setCopy(CopyMI);
|
|
|
|
return VNI;
|
|
|
|
}
|
|
|
|
|
2010-09-16 08:01:36 +08:00
|
|
|
/// Create a new virtual register and live interval.
|
|
|
|
void SplitEditor::openIntv() {
|
2011-02-03 14:18:29 +08:00
|
|
|
assert(!OpenIdx && "Previous LI not closed before openIntv");
|
2010-08-05 06:08:39 +08:00
|
|
|
|
2011-02-03 14:18:29 +08:00
|
|
|
// Create the complement as index 0.
|
2011-03-03 07:31:50 +08:00
|
|
|
if (Edit->empty())
|
|
|
|
Edit->create(MRI, LIS, VRM);
|
2011-02-03 14:18:29 +08:00
|
|
|
|
|
|
|
// Create the open interval.
|
2011-03-03 07:31:50 +08:00
|
|
|
OpenIdx = Edit->size();
|
|
|
|
Edit->create(MRI, LIS, VRM);
|
2010-07-27 07:44:11 +08:00
|
|
|
}
|
|
|
|
|
2011-02-04 01:04:16 +08:00
|
|
|
SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
|
2011-02-03 14:18:29 +08:00
|
|
|
assert(OpenIdx && "openIntv not called before enterIntvBefore");
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << " enterIntvBefore " << Idx);
|
2011-02-04 01:04:16 +08:00
|
|
|
Idx = Idx.getBaseIndex();
|
2011-03-03 07:31:50 +08:00
|
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
2010-09-16 08:01:36 +08:00
|
|
|
if (!ParentVNI) {
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << ": not live\n");
|
2011-02-04 01:04:16 +08:00
|
|
|
return Idx;
|
2010-08-13 01:07:14 +08:00
|
|
|
}
|
2011-02-04 01:04:16 +08:00
|
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
2011-01-26 08:50:53 +08:00
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
2010-09-16 08:01:36 +08:00
|
|
|
assert(MI && "enterIntvBefore called with invalid index");
|
2010-11-11 03:31:50 +08:00
|
|
|
|
2011-02-04 01:04:16 +08:00
|
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
|
|
|
|
return VNI->def;
|
2010-08-13 01:07:14 +08:00
|
|
|
}
|
|
|
|
|
2011-02-04 01:04:16 +08:00
|
|
|
SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
|
2011-02-03 14:18:29 +08:00
|
|
|
assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
|
2011-02-04 01:04:16 +08:00
|
|
|
SlotIndex End = LIS.getMBBEndIdx(&MBB);
|
|
|
|
SlotIndex Last = End.getPrevSlot();
|
|
|
|
DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
|
2011-03-03 07:31:50 +08:00
|
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
|
2010-09-16 08:01:36 +08:00
|
|
|
if (!ParentVNI) {
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << ": not live\n");
|
2011-02-04 01:04:16 +08:00
|
|
|
return End;
|
2010-07-27 07:44:11 +08:00
|
|
|
}
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id);
|
2011-02-04 01:04:16 +08:00
|
|
|
VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
|
2011-03-03 07:31:50 +08:00
|
|
|
LIS.getLastSplitPoint(Edit->getParent(), &MBB));
|
2011-02-04 01:04:16 +08:00
|
|
|
RegAssign.insert(VNI->def, End, OpenIdx);
|
2011-02-03 14:18:29 +08:00
|
|
|
DEBUG(dump());
|
2011-02-04 01:04:16 +08:00
|
|
|
return VNI->def;
|
2010-07-27 07:44:11 +08:00
|
|
|
}
|
|
|
|
|
2011-01-26 08:50:53 +08:00
|
|
|
/// useIntv - indicate that all instructions in MBB should use OpenLI.
|
2010-08-05 06:08:39 +08:00
|
|
|
void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
|
2011-01-26 08:50:53 +08:00
|
|
|
useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
|
2010-07-27 07:44:11 +08:00
|
|
|
}
|
|
|
|
|
2010-08-05 06:08:39 +08:00
|
|
|
void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
|
2011-02-03 14:18:29 +08:00
|
|
|
assert(OpenIdx && "openIntv not called before useIntv");
|
|
|
|
DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
|
|
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
|
|
DEBUG(dump());
|
2010-07-27 07:44:11 +08:00
|
|
|
}
|
|
|
|
|
2011-02-04 01:04:16 +08:00
|
|
|
SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
|
2011-02-03 14:18:29 +08:00
|
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAfter");
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << " leaveIntvAfter " << Idx);
|
2010-08-13 01:07:14 +08:00
|
|
|
|
2010-09-16 08:01:36 +08:00
|
|
|
// The interval must be live beyond the instruction at Idx.
|
2010-11-11 03:31:50 +08:00
|
|
|
Idx = Idx.getBoundaryIndex();
|
2011-03-03 07:31:50 +08:00
|
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
2010-09-16 08:01:36 +08:00
|
|
|
if (!ParentVNI) {
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << ": not live\n");
|
2011-02-04 01:04:16 +08:00
|
|
|
return Idx.getNextSlot();
|
2010-08-13 01:07:14 +08:00
|
|
|
}
|
2011-02-04 01:04:16 +08:00
|
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
2010-08-13 01:07:14 +08:00
|
|
|
|
2011-02-09 02:50:18 +08:00
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
|
|
assert(MI && "No instruction at index");
|
|
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)));
|
2011-02-04 01:04:16 +08:00
|
|
|
return VNI->def;
|
2010-08-13 01:07:14 +08:00
|
|
|
}
|
|
|
|
|
2011-02-10 07:30:25 +08:00
|
|
|
SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
|
|
|
|
assert(OpenIdx && "openIntv not called before leaveIntvBefore");
|
|
|
|
DEBUG(dbgs() << " leaveIntvBefore " << Idx);
|
|
|
|
|
|
|
|
// The interval must be live into the instruction at Idx.
|
|
|
|
Idx = Idx.getBoundaryIndex();
|
2011-03-03 07:31:50 +08:00
|
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
|
2011-02-10 07:30:25 +08:00
|
|
|
if (!ParentVNI) {
|
|
|
|
DEBUG(dbgs() << ": not live\n");
|
|
|
|
return Idx.getNextSlot();
|
|
|
|
}
|
|
|
|
DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
|
|
|
|
|
|
|
|
MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
|
|
|
|
assert(MI && "No instruction at index");
|
|
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
|
|
|
|
return VNI->def;
|
|
|
|
}
|
|
|
|
|
2011-02-04 01:04:16 +08:00
|
|
|
SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
|
2011-02-03 14:18:29 +08:00
|
|
|
assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
|
2011-01-26 08:50:53 +08:00
|
|
|
SlotIndex Start = LIS.getMBBStartIdx(&MBB);
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
|
2010-08-05 06:08:39 +08:00
|
|
|
|
2011-03-03 07:31:50 +08:00
|
|
|
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
|
2010-09-16 08:01:36 +08:00
|
|
|
if (!ParentVNI) {
|
2010-10-08 01:56:35 +08:00
|
|
|
DEBUG(dbgs() << ": not live\n");
|
2011-02-04 01:04:16 +08:00
|
|
|
return Start;
|
2010-08-05 06:08:39 +08:00
|
|
|
}
|
|
|
|
|
2011-02-03 14:18:29 +08:00
|
|
|
VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
|
2010-11-11 03:31:50 +08:00
|
|
|
MBB.SkipPHIsAndLabels(MBB.begin()));
|
2011-02-03 14:18:29 +08:00
|
|
|
RegAssign.insert(Start, VNI->def, OpenIdx);
|
|
|
|
DEBUG(dump());
|
2011-02-04 01:04:16 +08:00
|
|
|
return VNI->def;
|
2010-07-27 07:44:11 +08:00
|
|
|
}
|
|
|
|
|
2011-02-09 02:50:21 +08:00
|
|
|
void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
|
|
|
|
assert(OpenIdx && "openIntv not called before overlapIntv");
|
2011-03-03 07:31:50 +08:00
|
|
|
const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
|
|
|
|
assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
|
2011-02-09 02:50:21 +08:00
|
|
|
"Parent changes value in extended range");
|
|
|
|
assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
|
|
|
|
"Range cannot span basic blocks");
|
|
|
|
|
2011-03-02 08:49:28 +08:00
|
|
|
// The complement interval will be extended as needed by extendRange().
|
2011-03-03 07:05:19 +08:00
|
|
|
markComplexMapped(0, ParentVNI);
|
2011-02-09 02:50:21 +08:00
|
|
|
DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
|
|
|
|
RegAssign.insert(Start, End, OpenIdx);
|
|
|
|
DEBUG(dump());
|
|
|
|
}
|
|
|
|
|
2010-08-05 06:08:39 +08:00
|
|
|
/// closeIntv - Indicate that we are done editing the currently open
|
2010-07-27 07:44:11 +08:00
|
|
|
/// LiveInterval, and ranges can be trimmed.
|
2010-08-05 06:08:39 +08:00
|
|
|
void SplitEditor::closeIntv() {
|
2011-02-03 14:18:29 +08:00
|
|
|
assert(OpenIdx && "openIntv not called before closeIntv");
|
|
|
|
OpenIdx = 0;
|
2010-09-22 06:32:21 +08:00
|
|
|
}
|
2010-08-05 06:08:39 +08:00
|
|
|
|
2011-03-03 07:05:19 +08:00
|
|
|
/// transferSimpleValues - Transfer all simply defined values to the new live
|
|
|
|
/// ranges.
|
|
|
|
/// Values that were rematerialized or that have multiple defs are left alone.
|
|
|
|
bool SplitEditor::transferSimpleValues() {
|
|
|
|
bool Skipped = false;
|
|
|
|
RegAssignMap::const_iterator AssignI = RegAssign.begin();
|
2011-03-03 07:31:50 +08:00
|
|
|
for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
|
|
|
|
ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
|
2011-03-03 07:05:19 +08:00
|
|
|
DEBUG(dbgs() << " blit " << *ParentI << ':');
|
|
|
|
VNInfo *ParentVNI = ParentI->valno;
|
|
|
|
// RegAssign has holes where RegIdx 0 should be used.
|
|
|
|
SlotIndex Start = ParentI->start;
|
|
|
|
AssignI.advanceTo(Start);
|
|
|
|
do {
|
|
|
|
unsigned RegIdx;
|
|
|
|
SlotIndex End = ParentI->end;
|
|
|
|
if (!AssignI.valid()) {
|
|
|
|
RegIdx = 0;
|
|
|
|
} else if (AssignI.start() <= Start) {
|
|
|
|
RegIdx = AssignI.value();
|
|
|
|
if (AssignI.stop() < End) {
|
|
|
|
End = AssignI.stop();
|
|
|
|
++AssignI;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
RegIdx = 0;
|
|
|
|
End = std::min(End, AssignI.start());
|
|
|
|
}
|
|
|
|
DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
|
|
|
|
if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
|
|
|
|
DEBUG(dbgs() << ':' << VNI->id);
|
2011-03-03 07:31:50 +08:00
|
|
|
Edit->get(RegIdx)->addRange(LiveRange(Start, End, VNI));
|
2011-03-03 07:05:19 +08:00
|
|
|
} else
|
|
|
|
Skipped = true;
|
|
|
|
Start = End;
|
|
|
|
} while (Start != ParentI->end);
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
}
|
|
|
|
return Skipped;
|
|
|
|
}
|
|
|
|
|
2011-03-03 07:05:16 +08:00
|
|
|
void SplitEditor::extendPHIKillRanges() {
|
|
|
|
// Extend live ranges to be live-out for successor PHI values.
|
2011-03-03 07:31:50 +08:00
|
|
|
for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
|
|
|
|
E = Edit->getParent().vni_end(); I != E; ++I) {
|
2011-03-03 07:05:16 +08:00
|
|
|
const VNInfo *PHIVNI = *I;
|
|
|
|
if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
|
|
|
|
continue;
|
|
|
|
unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
|
|
|
|
MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
|
|
|
|
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
|
|
|
PE = MBB->pred_end(); PI != PE; ++PI) {
|
|
|
|
SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
|
|
|
|
// The predecessor may not have a live-out value. That is OK, like an
|
|
|
|
// undef PHI operand.
|
2011-03-03 07:31:50 +08:00
|
|
|
if (Edit->getParent().liveAt(End)) {
|
2011-03-03 07:05:16 +08:00
|
|
|
assert(RegAssign.lookup(End) == RegIdx &&
|
|
|
|
"Different register assignment in phi predecessor");
|
|
|
|
extendRange(RegIdx, End);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-03 07:31:50 +08:00
|
|
|
/// rewriteAssigned - Rewrite all uses of Edit->getReg().
|
2011-03-03 07:05:19 +08:00
|
|
|
void SplitEditor::rewriteAssigned(bool ExtendRanges) {
|
2011-03-03 07:31:50 +08:00
|
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
|
2011-01-26 08:50:53 +08:00
|
|
|
RE = MRI.reg_end(); RI != RE;) {
|
2010-10-09 07:42:21 +08:00
|
|
|
MachineOperand &MO = RI.getOperand();
|
|
|
|
MachineInstr *MI = MO.getParent();
|
|
|
|
++RI;
|
2011-02-03 14:18:29 +08:00
|
|
|
// LiveDebugVariables should have handled all DBG_VALUE instructions.
|
2010-10-09 07:42:21 +08:00
|
|
|
if (MI->isDebugValue()) {
|
|
|
|
DEBUG(dbgs() << "Zapping " << *MI);
|
|
|
|
MO.setReg(0);
|
|
|
|
continue;
|
|
|
|
}
|
2011-02-10 05:52:09 +08:00
|
|
|
|
|
|
|
// <undef> operands don't really read the register, so just assign them to
|
|
|
|
// the complement.
|
|
|
|
if (MO.isUse() && MO.isUndef()) {
|
2011-03-03 07:31:50 +08:00
|
|
|
MO.setReg(Edit->get(0)->reg);
|
2011-02-10 05:52:09 +08:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2011-01-26 08:50:53 +08:00
|
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI);
|
2010-10-09 07:42:21 +08:00
|
|
|
Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
|
2011-02-03 14:18:29 +08:00
|
|
|
|
|
|
|
// Rewrite to the mapped register at Idx.
|
|
|
|
unsigned RegIdx = RegAssign.lookup(Idx);
|
2011-03-03 07:31:50 +08:00
|
|
|
MO.setReg(Edit->get(RegIdx)->reg);
|
2011-02-03 14:18:29 +08:00
|
|
|
DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
|
|
|
|
<< Idx << ':' << RegIdx << '\t' << *MI);
|
|
|
|
|
|
|
|
// Extend liveness to Idx.
|
2011-03-03 07:05:19 +08:00
|
|
|
if (ExtendRanges)
|
|
|
|
extendRange(RegIdx, Idx);
|
2010-10-09 07:42:21 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-02-03 14:18:29 +08:00
|
|
|
/// rewriteSplit - Rewrite uses of Intvs[0] according to the ConEQ mapping.
|
|
|
|
void SplitEditor::rewriteComponents(const SmallVectorImpl<LiveInterval*> &Intvs,
|
|
|
|
const ConnectedVNInfoEqClasses &ConEq) {
|
|
|
|
for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Intvs[0]->reg),
|
|
|
|
RE = MRI.reg_end(); RI != RE;) {
|
|
|
|
MachineOperand &MO = RI.getOperand();
|
|
|
|
MachineInstr *MI = MO.getParent();
|
|
|
|
++RI;
|
|
|
|
if (MO.isUse() && MO.isUndef())
|
2010-10-22 02:47:08 +08:00
|
|
|
continue;
|
2011-02-03 14:18:29 +08:00
|
|
|
// DBG_VALUE instructions should have been eliminated earlier.
|
|
|
|
SlotIndex Idx = LIS.getInstructionIndex(MI);
|
|
|
|
Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
|
|
|
|
DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
|
|
|
|
<< Idx << ':');
|
|
|
|
const VNInfo *VNI = Intvs[0]->getVNInfoAt(Idx);
|
|
|
|
assert(VNI && "Interval not live at use.");
|
|
|
|
MO.setReg(Intvs[ConEq.getEqClass(VNI)]->reg);
|
|
|
|
DEBUG(dbgs() << VNI->id << '\t' << *MI);
|
2010-09-22 06:32:21 +08:00
|
|
|
}
|
2011-02-03 13:40:54 +08:00
|
|
|
}
|
2010-09-22 06:32:21 +08:00
|
|
|
|
2011-02-03 14:18:29 +08:00
|
|
|
void SplitEditor::finish() {
|
|
|
|
assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
|
2011-03-03 07:05:19 +08:00
|
|
|
++NumFinished;
|
2011-02-03 14:18:29 +08:00
|
|
|
|
|
|
|
// At this point, the live intervals in Edit contain VNInfos corresponding to
|
|
|
|
// the inserted copies.
|
|
|
|
|
|
|
|
// Add the original defs from the parent interval.
|
2011-03-03 07:31:50 +08:00
|
|
|
for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
|
|
|
|
E = Edit->getParent().vni_end(); I != E; ++I) {
|
2011-02-03 14:18:29 +08:00
|
|
|
const VNInfo *ParentVNI = *I;
|
2011-02-04 08:59:23 +08:00
|
|
|
if (ParentVNI->isUnused())
|
|
|
|
continue;
|
2011-03-02 07:14:53 +08:00
|
|
|
unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
|
|
|
|
defValue(RegIdx, ParentVNI, ParentVNI->def);
|
2011-03-03 07:05:19 +08:00
|
|
|
// Mark rematted values as complex everywhere to force liveness computation.
|
|
|
|
// The new live ranges may be truncated.
|
2011-03-03 07:31:50 +08:00
|
|
|
if (Edit->didRematerialize(ParentVNI))
|
|
|
|
for (unsigned i = 0, e = Edit->size(); i != e; ++i)
|
2011-03-03 07:05:19 +08:00
|
|
|
markComplexMapped(i, ParentVNI);
|
2010-09-22 06:32:21 +08:00
|
|
|
}
|
2010-10-27 08:39:07 +08:00
|
|
|
|
2011-02-03 14:18:29 +08:00
|
|
|
#ifndef NDEBUG
|
|
|
|
// Every new interval must have a def by now, otherwise the split is bogus.
|
2011-03-03 07:31:50 +08:00
|
|
|
for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
|
2011-02-03 14:18:29 +08:00
|
|
|
assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
|
|
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#endif
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2011-03-03 07:05:19 +08:00
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// Transfer the simply mapped values, check if any are complex.
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bool Complex = transferSimpleValues();
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if (Complex)
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extendPHIKillRanges();
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else
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++NumSimple;
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// Rewrite virtual registers, possibly extending ranges.
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rewriteAssigned(Complex);
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2011-02-03 13:40:54 +08:00
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2011-02-03 14:18:29 +08:00
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// FIXME: Delete defs that were rematted everywhere.
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2010-09-22 06:32:21 +08:00
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2010-10-08 07:34:34 +08:00
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// Get rid of unused values and set phi-kill flags.
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2011-03-03 07:31:50 +08:00
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for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
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2011-01-26 08:50:53 +08:00
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(*I)->RenumberValues(LIS);
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2010-10-08 07:34:34 +08:00
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2010-10-27 06:36:09 +08:00
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// Now check if any registers were separated into multiple components.
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2011-01-26 08:50:53 +08:00
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ConnectedVNInfoEqClasses ConEQ(LIS);
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2011-03-03 07:31:50 +08:00
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for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
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2010-10-27 06:36:09 +08:00
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// Don't use iterators, they are invalidated by create() below.
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2011-03-03 07:31:50 +08:00
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LiveInterval *li = Edit->get(i);
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2010-10-27 06:36:09 +08:00
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unsigned NumComp = ConEQ.Classify(li);
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if (NumComp <= 1)
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continue;
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DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
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SmallVector<LiveInterval*, 8> dups;
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dups.push_back(li);
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for (unsigned i = 1; i != NumComp; ++i)
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2011-03-03 07:31:50 +08:00
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dups.push_back(&Edit->create(MRI, LIS, VRM));
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2011-02-03 14:18:29 +08:00
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rewriteComponents(dups, ConEQ);
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2010-10-27 06:36:09 +08:00
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ConEQ.Distribute(&dups[0]);
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}
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2010-08-11 01:07:22 +08:00
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// Calculate spill weight and allocation hints for new intervals.
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2011-02-19 08:42:33 +08:00
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VirtRegAuxInfo vrai(VRM.getMachineFunction(), LIS, SA.Loops);
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2011-03-03 07:31:50 +08:00
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for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
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2010-10-15 07:49:52 +08:00
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LiveInterval &li = **I;
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2010-08-11 02:37:40 +08:00
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vrai.CalculateRegClass(li.reg);
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2010-08-11 01:07:22 +08:00
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vrai.CalculateWeightAndHint(li);
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2011-01-26 08:50:53 +08:00
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DEBUG(dbgs() << " new interval " << MRI.getRegClass(li.reg)->getName()
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2010-08-13 02:50:55 +08:00
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<< ":" << li << '\n');
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2010-08-11 01:07:22 +08:00
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}
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2010-07-27 07:44:11 +08:00
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}
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2010-08-13 01:07:14 +08:00
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//===----------------------------------------------------------------------===//
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// Single Block Splitting
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//===----------------------------------------------------------------------===//
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2011-01-26 08:50:53 +08:00
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/// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
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/// may be an advantage to split CurLI for the duration of the block.
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2010-10-23 06:48:56 +08:00
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bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
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2011-01-26 08:50:53 +08:00
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// If CurLI is local to one block, there is no point to splitting it.
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2011-02-10 07:30:25 +08:00
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if (LiveBlocks.size() <= 1)
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2010-10-23 06:48:56 +08:00
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return false;
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// Add blocks with multiple uses.
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2011-02-10 07:30:25 +08:00
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for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
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const BlockInfo &BI = LiveBlocks[i];
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if (!BI.Uses)
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2010-10-23 06:48:56 +08:00
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continue;
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2011-02-10 07:30:25 +08:00
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unsigned Instrs = UsingBlocks.lookup(BI.MBB);
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if (Instrs <= 1)
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continue;
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if (Instrs == 2 && BI.LiveIn && BI.LiveOut && !BI.LiveThrough)
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continue;
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Blocks.insert(BI.MBB);
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}
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2010-10-23 06:48:56 +08:00
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return !Blocks.empty();
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}
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2011-01-26 08:50:53 +08:00
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/// splitSingleBlocks - Split CurLI into a separate live interval inside each
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2010-10-06 06:19:33 +08:00
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|
/// basic block in Blocks.
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void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
|
2010-08-13 02:50:55 +08:00
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|
DEBUG(dbgs() << " splitSingleBlocks for " << Blocks.size() << " blocks.\n");
|
2010-08-13 01:07:14 +08:00
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|
2011-02-19 08:42:33 +08:00
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for (unsigned i = 0, e = SA.LiveBlocks.size(); i != e; ++i) {
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|
const SplitAnalysis::BlockInfo &BI = SA.LiveBlocks[i];
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2011-02-10 07:30:25 +08:00
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|
if (!BI.Uses || !Blocks.count(BI.MBB))
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|
continue;
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2010-08-13 01:07:14 +08:00
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|
|
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|
|
openIntv();
|
2011-02-10 07:30:25 +08:00
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|
|
SlotIndex SegStart = enterIntvBefore(BI.FirstUse);
|
2011-02-24 02:26:31 +08:00
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|
|
if (!BI.LiveOut || BI.LastUse < BI.LastSplitPoint) {
|
2011-02-10 07:30:25 +08:00
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|
|
useIntv(SegStart, leaveIntvAfter(BI.LastUse));
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|
} else {
|
2011-02-24 02:26:31 +08:00
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|
|
// The last use is after the last valid split point.
|
2011-02-10 07:30:25 +08:00
|
|
|
SlotIndex SegStop = leaveIntvBefore(BI.LastSplitPoint);
|
|
|
|
useIntv(SegStart, SegStop);
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|
|
|
overlapIntv(SegStop, BI.LastUse);
|
|
|
|
}
|
2010-08-13 01:07:14 +08:00
|
|
|
closeIntv();
|
|
|
|
}
|
2010-10-09 07:42:21 +08:00
|
|
|
finish();
|
2010-08-13 01:07:14 +08:00
|
|
|
}
|