2018-10-10 06:03:40 +08:00
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//===---- X86CondBrFolding.cpp - optimize conditional branches ------------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2018-10-10 06:03:40 +08:00
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//
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//===----------------------------------------------------------------------===//
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// This file defines a pass that optimizes condition branches on x86 by taking
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// advantage of the three-way conditional code generated by compare
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// instructions.
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// Currently, it tries to hoisting EQ and NE conditional branch to a dominant
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// conditional branch condition where the same EQ/NE conditional code is
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// computed. An example:
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// bb_0:
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// cmp %0, 19
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// jg bb_1
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// jmp bb_2
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// bb_1:
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// cmp %0, 40
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// jg bb_3
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// jmp bb_4
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// bb_4:
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// cmp %0, 20
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// je bb_5
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// jmp bb_6
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// Here we could combine the two compares in bb_0 and bb_4 and have the
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// following code:
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// bb_0:
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// cmp %0, 20
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// jg bb_1
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// jl bb_2
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// jmp bb_5
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// bb_1:
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// cmp %0, 40
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// jg bb_3
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// jmp bb_6
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// For the case of %0 == 20 (bb_5), we eliminate two jumps, and the control
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// height for bb_6 is also reduced. bb_4 is gone after the optimization.
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//
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// There are plenty of this code patterns, especially from the switch case
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// lowing where we generate compare of "pivot-1" for the inner nodes in the
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// binary search tree.
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/BranchProbability.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-condbr-folding"
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STATISTIC(NumFixedCondBrs, "Number of x86 condbr folded");
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namespace {
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class X86CondBrFoldingPass : public MachineFunctionPass {
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public:
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2019-06-13 10:09:32 +08:00
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X86CondBrFoldingPass() : MachineFunctionPass(ID) { }
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2018-10-10 06:03:40 +08:00
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StringRef getPassName() const override { return "X86 CondBr Folding"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<MachineBranchProbabilityInfo>();
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}
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2018-12-08 02:10:34 +08:00
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public:
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2018-10-10 06:03:40 +08:00
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static char ID;
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};
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2018-12-08 02:10:34 +08:00
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} // namespace
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2018-10-10 06:03:40 +08:00
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char X86CondBrFoldingPass::ID = 0;
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2018-12-08 02:10:34 +08:00
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INITIALIZE_PASS(X86CondBrFoldingPass, "X86CondBrFolding", "X86CondBrFolding", false, false)
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2018-10-10 06:03:40 +08:00
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FunctionPass *llvm::createX86CondBrFolding() {
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return new X86CondBrFoldingPass();
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}
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2018-10-14 06:18:22 +08:00
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namespace {
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2018-10-10 06:03:40 +08:00
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// A class the stores the auxiliary information for each MBB.
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struct TargetMBBInfo {
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MachineBasicBlock *TBB;
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MachineBasicBlock *FBB;
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MachineInstr *BrInstr;
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MachineInstr *CmpInstr;
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X86::CondCode BranchCode;
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unsigned SrcReg;
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int CmpValue;
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bool Modified;
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bool CmpBrOnly;
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};
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// A class that optimizes the conditional branch by hoisting and merge CondCode.
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class X86CondBrFolding {
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public:
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X86CondBrFolding(const X86InstrInfo *TII,
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const MachineBranchProbabilityInfo *MBPI,
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MachineFunction &MF)
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: TII(TII), MBPI(MBPI), MF(MF) {}
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bool optimize();
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private:
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const X86InstrInfo *TII;
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const MachineBranchProbabilityInfo *MBPI;
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MachineFunction &MF;
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std::vector<std::unique_ptr<TargetMBBInfo>> MBBInfos;
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SmallVector<MachineBasicBlock *, 4> RemoveList;
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void optimizeCondBr(MachineBasicBlock &MBB,
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SmallVectorImpl<MachineBasicBlock *> &BranchPath);
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void fixBranchProb(MachineBasicBlock *NextMBB, MachineBasicBlock *RootMBB,
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SmallVectorImpl<MachineBasicBlock *> &BranchPath);
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void replaceBrDest(MachineBasicBlock *MBB, MachineBasicBlock *OrigDest,
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MachineBasicBlock *NewDest);
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void fixupModifiedCond(MachineBasicBlock *MBB);
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std::unique_ptr<TargetMBBInfo> analyzeMBB(MachineBasicBlock &MBB);
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static bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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int &CmpValue);
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bool findPath(MachineBasicBlock *MBB,
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SmallVectorImpl<MachineBasicBlock *> &BranchPath);
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TargetMBBInfo *getMBBInfo(MachineBasicBlock *MBB) const {
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return MBBInfos[MBB->getNumber()].get();
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}
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};
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2018-10-14 06:18:22 +08:00
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} // namespace
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2018-10-10 06:03:40 +08:00
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// Find a valid path that we can reuse the CondCode.
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// The resulted path (if return true) is stored in BranchPath.
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// Return value:
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// false: is no valid path is found.
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// true: a valid path is found and the targetBB can be reached.
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bool X86CondBrFolding::findPath(
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MachineBasicBlock *MBB, SmallVectorImpl<MachineBasicBlock *> &BranchPath) {
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TargetMBBInfo *MBBInfo = getMBBInfo(MBB);
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assert(MBBInfo && "Expecting a candidate MBB");
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int CmpValue = MBBInfo->CmpValue;
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MachineBasicBlock *PredMBB = *MBB->pred_begin();
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MachineBasicBlock *SaveMBB = MBB;
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while (PredMBB) {
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TargetMBBInfo *PredMBBInfo = getMBBInfo(PredMBB);
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if (!PredMBBInfo || PredMBBInfo->SrcReg != MBBInfo->SrcReg)
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return false;
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assert(SaveMBB == PredMBBInfo->TBB || SaveMBB == PredMBBInfo->FBB);
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bool IsFalseBranch = (SaveMBB == PredMBBInfo->FBB);
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X86::CondCode CC = PredMBBInfo->BranchCode;
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assert(CC == X86::COND_L || CC == X86::COND_G || CC == X86::COND_E);
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int PredCmpValue = PredMBBInfo->CmpValue;
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bool ValueCmpTrue = ((CmpValue < PredCmpValue && CC == X86::COND_L) ||
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(CmpValue > PredCmpValue && CC == X86::COND_G) ||
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(CmpValue == PredCmpValue && CC == X86::COND_E));
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// Check if both the result of value compare and the branch target match.
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if (!(ValueCmpTrue ^ IsFalseBranch)) {
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LLVM_DEBUG(dbgs() << "Dead BB detected!\n");
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return false;
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}
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BranchPath.push_back(PredMBB);
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// These are the conditions on which we could combine the compares.
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if ((CmpValue == PredCmpValue) ||
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(CmpValue == PredCmpValue - 1 && CC == X86::COND_L) ||
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(CmpValue == PredCmpValue + 1 && CC == X86::COND_G))
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return true;
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// If PredMBB has more than on preds, or not a pure cmp and br, we bailout.
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if (PredMBB->pred_size() != 1 || !PredMBBInfo->CmpBrOnly)
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return false;
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SaveMBB = PredMBB;
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PredMBB = *PredMBB->pred_begin();
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}
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return false;
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}
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// Fix up any PHI node in the successor of MBB.
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static void fixPHIsInSucc(MachineBasicBlock *MBB, MachineBasicBlock *OldMBB,
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MachineBasicBlock *NewMBB) {
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if (NewMBB == OldMBB)
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return;
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for (auto MI = MBB->instr_begin(), ME = MBB->instr_end();
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MI != ME && MI->isPHI(); ++MI)
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for (unsigned i = 2, e = MI->getNumOperands() + 1; i != e; i += 2) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.getMBB() == OldMBB)
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MO.setMBB(NewMBB);
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}
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}
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// Utility function to set branch probability for edge MBB->SuccMBB.
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static inline bool setBranchProb(MachineBasicBlock *MBB,
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MachineBasicBlock *SuccMBB,
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BranchProbability Prob) {
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auto MBBI = std::find(MBB->succ_begin(), MBB->succ_end(), SuccMBB);
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if (MBBI == MBB->succ_end())
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return false;
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MBB->setSuccProbability(MBBI, Prob);
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return true;
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}
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// Utility function to find the unconditional br instruction in MBB.
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static inline MachineBasicBlock::iterator
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findUncondBrI(MachineBasicBlock *MBB) {
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return std::find_if(MBB->begin(), MBB->end(), [](MachineInstr &MI) -> bool {
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return MI.getOpcode() == X86::JMP_1;
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});
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}
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// Replace MBB's original successor, OrigDest, with NewDest.
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// Also update the MBBInfo for MBB.
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void X86CondBrFolding::replaceBrDest(MachineBasicBlock *MBB,
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MachineBasicBlock *OrigDest,
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MachineBasicBlock *NewDest) {
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TargetMBBInfo *MBBInfo = getMBBInfo(MBB);
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MachineInstr *BrMI;
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if (MBBInfo->TBB == OrigDest) {
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BrMI = MBBInfo->BrInstr;
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MachineInstrBuilder MIB =
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(X86::JCC_1))
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.addMBB(NewDest).addImm(MBBInfo->BranchCode);
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2018-10-10 06:03:40 +08:00
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MBBInfo->TBB = NewDest;
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MBBInfo->BrInstr = MIB.getInstr();
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} else { // Should be the unconditional jump stmt.
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MachineBasicBlock::iterator UncondBrI = findUncondBrI(MBB);
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BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
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.addMBB(NewDest);
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MBBInfo->FBB = NewDest;
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BrMI = &*UncondBrI;
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}
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fixPHIsInSucc(NewDest, OrigDest, MBB);
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BrMI->eraseFromParent();
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MBB->addSuccessor(NewDest);
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setBranchProb(MBB, NewDest, MBPI->getEdgeProbability(MBB, OrigDest));
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MBB->removeSuccessor(OrigDest);
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}
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// Change the CondCode and BrInstr according to MBBInfo.
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void X86CondBrFolding::fixupModifiedCond(MachineBasicBlock *MBB) {
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TargetMBBInfo *MBBInfo = getMBBInfo(MBB);
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if (!MBBInfo->Modified)
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return;
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MachineInstr *BrMI = MBBInfo->BrInstr;
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X86::CondCode CC = MBBInfo->BranchCode;
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MachineInstrBuilder MIB = BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI),
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[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
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TII->get(X86::JCC_1))
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.addMBB(MBBInfo->TBB).addImm(CC);
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2018-10-10 06:03:40 +08:00
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BrMI->eraseFromParent();
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MBBInfo->BrInstr = MIB.getInstr();
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MachineBasicBlock::iterator UncondBrI = findUncondBrI(MBB);
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BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
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.addMBB(MBBInfo->FBB);
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MBB->erase(UncondBrI);
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MBBInfo->Modified = false;
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}
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//
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// Apply the transformation:
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// RootMBB -1-> ... PredMBB -3-> MBB -5-> TargetMBB
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// \-2-> \-4-> \-6-> FalseMBB
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// ==>
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// RootMBB -1-> ... PredMBB -7-> FalseMBB
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// TargetMBB <-8-/ \-2-> \-4->
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//
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// Note that PredMBB and RootMBB could be the same.
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// And in the case of dead TargetMBB, we will not have TargetMBB and edge 8.
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//
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// There are some special handling where the RootMBB is COND_E in which case
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// we directly short-cycle the brinstr.
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//
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void X86CondBrFolding::optimizeCondBr(
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MachineBasicBlock &MBB, SmallVectorImpl<MachineBasicBlock *> &BranchPath) {
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X86::CondCode CC;
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TargetMBBInfo *MBBInfo = getMBBInfo(&MBB);
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assert(MBBInfo && "Expecting a candidate MBB");
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MachineBasicBlock *TargetMBB = MBBInfo->TBB;
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BranchProbability TargetProb = MBPI->getEdgeProbability(&MBB, MBBInfo->TBB);
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// Forward the jump from MBB's predecessor to MBB's false target.
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MachineBasicBlock *PredMBB = BranchPath.front();
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TargetMBBInfo *PredMBBInfo = getMBBInfo(PredMBB);
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assert(PredMBBInfo && "Expecting a candidate MBB");
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if (PredMBBInfo->Modified)
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fixupModifiedCond(PredMBB);
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CC = PredMBBInfo->BranchCode;
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// Don't do this if depth of BranchPath is 1 and PredMBB is of COND_E.
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// We will short-cycle directly for this case.
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if (!(CC == X86::COND_E && BranchPath.size() == 1))
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replaceBrDest(PredMBB, &MBB, MBBInfo->FBB);
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MachineBasicBlock *RootMBB = BranchPath.back();
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TargetMBBInfo *RootMBBInfo = getMBBInfo(RootMBB);
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assert(RootMBBInfo && "Expecting a candidate MBB");
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if (RootMBBInfo->Modified)
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fixupModifiedCond(RootMBB);
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CC = RootMBBInfo->BranchCode;
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|
|
|
if (CC != X86::COND_E) {
|
|
|
|
MachineBasicBlock::iterator UncondBrI = findUncondBrI(RootMBB);
|
|
|
|
// RootMBB: Cond jump to the original not-taken MBB.
|
|
|
|
X86::CondCode NewCC;
|
|
|
|
switch (CC) {
|
|
|
|
case X86::COND_L:
|
|
|
|
NewCC = X86::COND_G;
|
|
|
|
break;
|
|
|
|
case X86::COND_G:
|
|
|
|
NewCC = X86::COND_L;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
llvm_unreachable("unexpected condtional code.");
|
|
|
|
}
|
|
|
|
BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
TII->get(X86::JCC_1))
|
|
|
|
.addMBB(RootMBBInfo->FBB).addImm(NewCC);
|
2018-10-10 06:03:40 +08:00
|
|
|
|
|
|
|
// RootMBB: Jump to TargetMBB
|
|
|
|
BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
|
|
|
|
TII->get(X86::JMP_1))
|
|
|
|
.addMBB(TargetMBB);
|
|
|
|
RootMBB->addSuccessor(TargetMBB);
|
|
|
|
fixPHIsInSucc(TargetMBB, &MBB, RootMBB);
|
|
|
|
RootMBB->erase(UncondBrI);
|
|
|
|
} else {
|
|
|
|
replaceBrDest(RootMBB, RootMBBInfo->TBB, TargetMBB);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Fix RootMBB's CmpValue to MBB's CmpValue to TargetMBB. Don't set Imm
|
|
|
|
// directly. Move MBB's stmt to here as the opcode might be different.
|
|
|
|
if (RootMBBInfo->CmpValue != MBBInfo->CmpValue) {
|
|
|
|
MachineInstr *NewCmp = MBBInfo->CmpInstr;
|
|
|
|
NewCmp->removeFromParent();
|
|
|
|
RootMBB->insert(RootMBBInfo->CmpInstr, NewCmp);
|
|
|
|
RootMBBInfo->CmpInstr->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Fix branch Probabilities.
|
|
|
|
auto fixBranchProb = [&](MachineBasicBlock *NextMBB) {
|
|
|
|
BranchProbability Prob;
|
|
|
|
for (auto &I : BranchPath) {
|
|
|
|
MachineBasicBlock *ThisMBB = I;
|
|
|
|
if (!ThisMBB->hasSuccessorProbabilities() ||
|
|
|
|
!ThisMBB->isSuccessor(NextMBB))
|
|
|
|
break;
|
|
|
|
Prob = MBPI->getEdgeProbability(ThisMBB, NextMBB);
|
|
|
|
if (Prob.isUnknown())
|
|
|
|
break;
|
|
|
|
TargetProb = Prob * TargetProb;
|
|
|
|
Prob = Prob - TargetProb;
|
|
|
|
setBranchProb(ThisMBB, NextMBB, Prob);
|
|
|
|
if (ThisMBB == RootMBB) {
|
|
|
|
setBranchProb(ThisMBB, TargetMBB, TargetProb);
|
|
|
|
}
|
|
|
|
ThisMBB->normalizeSuccProbs();
|
|
|
|
if (ThisMBB == RootMBB)
|
|
|
|
break;
|
|
|
|
NextMBB = ThisMBB;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
};
|
|
|
|
if (CC != X86::COND_E && !TargetProb.isUnknown())
|
|
|
|
fixBranchProb(MBBInfo->FBB);
|
|
|
|
|
|
|
|
if (CC != X86::COND_E)
|
|
|
|
RemoveList.push_back(&MBB);
|
|
|
|
|
|
|
|
// Invalidate MBBInfo just in case.
|
|
|
|
MBBInfos[MBB.getNumber()] = nullptr;
|
|
|
|
MBBInfos[RootMBB->getNumber()] = nullptr;
|
|
|
|
|
|
|
|
LLVM_DEBUG(dbgs() << "After optimization:\nRootMBB is: " << *RootMBB << "\n");
|
|
|
|
if (BranchPath.size() > 1)
|
|
|
|
LLVM_DEBUG(dbgs() << "PredMBB is: " << *(BranchPath[0]) << "\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
// Driver function for optimization: find the valid candidate and apply
|
|
|
|
// the transformation.
|
|
|
|
bool X86CondBrFolding::optimize() {
|
|
|
|
bool Changed = false;
|
|
|
|
LLVM_DEBUG(dbgs() << "***** X86CondBr Folding on Function: " << MF.getName()
|
|
|
|
<< " *****\n");
|
|
|
|
// Setup data structures.
|
|
|
|
MBBInfos.resize(MF.getNumBlockIDs());
|
|
|
|
for (auto &MBB : MF)
|
|
|
|
MBBInfos[MBB.getNumber()] = analyzeMBB(MBB);
|
|
|
|
|
|
|
|
for (auto &MBB : MF) {
|
|
|
|
TargetMBBInfo *MBBInfo = getMBBInfo(&MBB);
|
|
|
|
if (!MBBInfo || !MBBInfo->CmpBrOnly)
|
|
|
|
continue;
|
|
|
|
if (MBB.pred_size() != 1)
|
|
|
|
continue;
|
|
|
|
LLVM_DEBUG(dbgs() << "Work on MBB." << MBB.getNumber()
|
|
|
|
<< " CmpValue: " << MBBInfo->CmpValue << "\n");
|
|
|
|
SmallVector<MachineBasicBlock *, 4> BranchPath;
|
|
|
|
if (!findPath(&MBB, BranchPath))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
LLVM_DEBUG(dbgs() << "Found one path (len=" << BranchPath.size() << "):\n");
|
|
|
|
int Index = 1;
|
|
|
|
LLVM_DEBUG(dbgs() << "Target MBB is: " << MBB << "\n");
|
|
|
|
for (auto I = BranchPath.rbegin(); I != BranchPath.rend(); ++I, ++Index) {
|
|
|
|
MachineBasicBlock *PMBB = *I;
|
|
|
|
TargetMBBInfo *PMBBInfo = getMBBInfo(PMBB);
|
|
|
|
LLVM_DEBUG(dbgs() << "Path MBB (" << Index << " of " << BranchPath.size()
|
|
|
|
<< ") is " << *PMBB);
|
|
|
|
LLVM_DEBUG(dbgs() << "CC=" << PMBBInfo->BranchCode
|
|
|
|
<< " Val=" << PMBBInfo->CmpValue
|
|
|
|
<< " CmpBrOnly=" << PMBBInfo->CmpBrOnly << "\n\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
optimizeCondBr(MBB, BranchPath);
|
|
|
|
Changed = true;
|
|
|
|
}
|
|
|
|
NumFixedCondBrs += RemoveList.size();
|
|
|
|
for (auto MBBI : RemoveList) {
|
2018-10-10 07:10:56 +08:00
|
|
|
while (!MBBI->succ_empty())
|
|
|
|
MBBI->removeSuccessor(MBBI->succ_end() - 1);
|
|
|
|
|
2018-10-10 06:03:40 +08:00
|
|
|
MBBI->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Analyze instructions that generate CondCode and extract information.
|
|
|
|
bool X86CondBrFolding::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
|
|
|
|
int &CmpValue) {
|
|
|
|
unsigned SrcRegIndex = 0;
|
|
|
|
unsigned ValueIndex = 0;
|
|
|
|
switch (MI.getOpcode()) {
|
|
|
|
// TODO: handle test instructions.
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case X86::CMP64ri32:
|
|
|
|
case X86::CMP64ri8:
|
|
|
|
case X86::CMP32ri:
|
|
|
|
case X86::CMP32ri8:
|
|
|
|
case X86::CMP16ri:
|
|
|
|
case X86::CMP16ri8:
|
|
|
|
case X86::CMP8ri:
|
|
|
|
SrcRegIndex = 0;
|
|
|
|
ValueIndex = 1;
|
|
|
|
break;
|
|
|
|
case X86::SUB64ri32:
|
|
|
|
case X86::SUB64ri8:
|
|
|
|
case X86::SUB32ri:
|
|
|
|
case X86::SUB32ri8:
|
|
|
|
case X86::SUB16ri:
|
|
|
|
case X86::SUB16ri8:
|
|
|
|
case X86::SUB8ri:
|
|
|
|
SrcRegIndex = 1;
|
|
|
|
ValueIndex = 2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
SrcReg = MI.getOperand(SrcRegIndex).getReg();
|
2018-12-11 23:32:14 +08:00
|
|
|
if (!MI.getOperand(ValueIndex).isImm())
|
|
|
|
return false;
|
2018-10-10 06:03:40 +08:00
|
|
|
CmpValue = MI.getOperand(ValueIndex).getImm();
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Analyze a candidate MBB and set the extract all the information needed.
|
|
|
|
// The valid candidate will have two successors.
|
|
|
|
// It also should have a sequence of
|
|
|
|
// Branch_instr,
|
|
|
|
// CondBr,
|
|
|
|
// UnCondBr.
|
|
|
|
// Return TargetMBBInfo if MBB is a valid candidate and nullptr otherwise.
|
|
|
|
std::unique_ptr<TargetMBBInfo>
|
|
|
|
X86CondBrFolding::analyzeMBB(MachineBasicBlock &MBB) {
|
|
|
|
MachineBasicBlock *TBB;
|
|
|
|
MachineBasicBlock *FBB;
|
|
|
|
MachineInstr *BrInstr;
|
|
|
|
MachineInstr *CmpInstr;
|
|
|
|
X86::CondCode CC;
|
|
|
|
unsigned SrcReg;
|
|
|
|
int CmpValue;
|
|
|
|
bool Modified;
|
|
|
|
bool CmpBrOnly;
|
|
|
|
|
|
|
|
if (MBB.succ_size() != 2)
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
CmpBrOnly = true;
|
|
|
|
FBB = TBB = nullptr;
|
|
|
|
CmpInstr = nullptr;
|
|
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
|
|
while (I != MBB.begin()) {
|
|
|
|
--I;
|
|
|
|
if (I->isDebugValue())
|
|
|
|
continue;
|
|
|
|
if (I->getOpcode() == X86::JMP_1) {
|
|
|
|
if (FBB)
|
|
|
|
return nullptr;
|
|
|
|
FBB = I->getOperand(0).getMBB();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (I->isBranch()) {
|
|
|
|
if (TBB)
|
|
|
|
return nullptr;
|
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
llvm-svn: 357802
2019-04-06 03:28:09 +08:00
|
|
|
CC = X86::getCondFromBranch(*I);
|
2018-10-10 06:03:40 +08:00
|
|
|
switch (CC) {
|
|
|
|
default:
|
|
|
|
return nullptr;
|
|
|
|
case X86::COND_E:
|
|
|
|
case X86::COND_L:
|
|
|
|
case X86::COND_G:
|
|
|
|
case X86::COND_NE:
|
|
|
|
case X86::COND_LE:
|
|
|
|
case X86::COND_GE:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
TBB = I->getOperand(0).getMBB();
|
|
|
|
BrInstr = &*I;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (analyzeCompare(*I, SrcReg, CmpValue)) {
|
|
|
|
if (CmpInstr)
|
|
|
|
return nullptr;
|
|
|
|
CmpInstr = &*I;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
CmpBrOnly = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!TBB || !FBB || !CmpInstr)
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
// Simplify CondCode. Note this is only to simplify the findPath logic
|
|
|
|
// and will not change the instruction here.
|
|
|
|
switch (CC) {
|
|
|
|
case X86::COND_NE:
|
|
|
|
CC = X86::COND_E;
|
|
|
|
std::swap(TBB, FBB);
|
|
|
|
Modified = true;
|
|
|
|
break;
|
|
|
|
case X86::COND_LE:
|
|
|
|
if (CmpValue == INT_MAX)
|
|
|
|
return nullptr;
|
|
|
|
CC = X86::COND_L;
|
|
|
|
CmpValue += 1;
|
|
|
|
Modified = true;
|
|
|
|
break;
|
|
|
|
case X86::COND_GE:
|
|
|
|
if (CmpValue == INT_MIN)
|
|
|
|
return nullptr;
|
|
|
|
CC = X86::COND_G;
|
|
|
|
CmpValue -= 1;
|
|
|
|
Modified = true;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
Modified = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return llvm::make_unique<TargetMBBInfo>(TargetMBBInfo{
|
|
|
|
TBB, FBB, BrInstr, CmpInstr, CC, SrcReg, CmpValue, Modified, CmpBrOnly});
|
|
|
|
}
|
|
|
|
|
|
|
|
bool X86CondBrFoldingPass::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
|
|
|
|
if (!ST.threewayBranchProfitable())
|
|
|
|
return false;
|
|
|
|
const X86InstrInfo *TII = ST.getInstrInfo();
|
|
|
|
const MachineBranchProbabilityInfo *MBPI =
|
|
|
|
&getAnalysis<MachineBranchProbabilityInfo>();
|
|
|
|
|
|
|
|
X86CondBrFolding CondBr(TII, MBPI, MF);
|
|
|
|
return CondBr.optimize();
|
|
|
|
}
|