forked from OSchip/llvm-project
46 lines
1.2 KiB
TableGen
46 lines
1.2 KiB
TableGen
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// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o %t
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// RUN: FileCheck %s < %t
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// Both predicates should be tested
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// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_b,
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// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_a,
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include "llvm/Target/Target.td"
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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def pat_frag_a : PatFrag <(ops node:$ptr), (load node:$ptr), [{}]> {
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let PredicateCode = [{ return isInstA(MI); }];
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let GISelPredicateCode = [{ return isInstA(MI); }];
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}
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def pat_frag_b : PatFrag <(ops node:$ptr), (load node:$ptr), [{}]> {
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let PredicateCode = [{ return isInstB(MI); }];
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let GISelPredicateCode = [{ return isInstB(MI); }];
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}
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def inst_a : Instruction {
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let OutOperandList = (outs GPR32:$dst);
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let InOperandList = (ins GPR32:$src);
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}
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def inst_b : Instruction {
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let OutOperandList = (outs GPR32:$dst);
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let InOperandList = (ins GPR32:$src);
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}
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def : Pat <
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(pat_frag_a GPR32:$src),
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(inst_a GPR32:$src)
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>;
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def : Pat <
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(pat_frag_b GPR32:$src),
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(inst_b GPR32:$src)
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>;
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