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llvm-project/llvm/test/CodeGen/X86/pr40529.ll

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[X86] Add test case from PR40529. NFC llvm-svn: 353138
2019-02-05 12:48:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Change the CPU on the test case for pr40529.ll to really show the bug. NFC llvm-svn: 353334
2019-02-07 03:50:59 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-linux -mcpu=x86-64 | FileCheck %s
[X86] Add test case from PR40529. NFC llvm-svn: 353138
2019-02-05 12:48:23 +08:00
define x86_fp80 @rem_pio2l_min(x86_fp80 %z) {
; CHECK-LABEL: rem_pio2l_min:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp)
[X86] Add FPCW as an implicit use on floating point load instructions. These instructions can generate a stack overflow exception so technically they read the stack overflow exception mask bit. llvm-svn: 353564
2019-02-09 04:50:09 +08:00
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
[X86] Add test case from PR40529. NFC llvm-svn: 353138
2019-02-05 12:48:23 +08:00
; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movw $3199, -{{[0-9]+}}(%rsp) # imm = 0xC7F
; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fistl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fisubl -{{[0-9]+}}(%rsp)
[X86] Change the CPU on the test case for pr40529.ll to really show the bug. NFC llvm-svn: 353334
2019-02-07 03:50:59 +08:00
; CHECK-NEXT: flds {{.*}}(%rip)
[X86] Add FPCW as a register and start using it as an implicit use on floating point instructions. Summary: FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence. This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529. Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor Subscribers: dim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57735 llvm-svn: 353489
2019-02-08 08:44:39 +08:00
; CHECK-NEXT: fnstcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fmul %st, %st(1)
[X86] Add test case from PR40529. NFC llvm-svn: 353138
2019-02-05 12:48:23 +08:00
; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movw $3199, -{{[0-9]+}}(%rsp) # imm = 0xC7F
; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fistl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fisubl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fmulp %st, %st(1)
; CHECK-NEXT: retq
entry:
%conv = fptosi x86_fp80 %z to i32
%conv1 = sitofp i32 %conv to x86_fp80
%sub = fsub x86_fp80 %z, %conv1
%mul = fmul x86_fp80 %sub, 0xK40178000000000000000
%conv2 = fptosi x86_fp80 %mul to i32
%conv3 = sitofp i32 %conv2 to x86_fp80
%sub4 = fsub x86_fp80 %mul, %conv3
%mul5 = fmul x86_fp80 %sub4, 0xK40178000000000000000
ret x86_fp80 %mul5
}