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llvm-project/llvm/lib/Target/AMDGPU/R600Processors.td

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AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
//===-- R600Processors.td - R600 Processor definitions --------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Radeon HD 2000/3000 Series (R600).
//===----------------------------------------------------------------------===//
def : Processor<"r600", R600_VLIW5_Itin,
[FeatureR600, FeatureWavefrontSize64, FeatureVertexCache]
>;
def : Processor<"r630", R600_VLIW5_Itin,
[FeatureR600, FeatureWavefrontSize32, FeatureVertexCache]
>;
def : Processor<"rs880", R600_VLIW5_Itin,
[FeatureR600, FeatureWavefrontSize16]
>;
def : Processor<"rv670", R600_VLIW5_Itin,
AMDGPU: Disable fp64 support on pre GCN asics It's not implemented. Passing +fp64-fp16-denormal feature enables fp64 even on asics that don't support it v2: fix hasFP64 query Differential Revision: https://reviews.llvm.org/D39931 llvm-svn: 319709
2017-12-05 06:57:29 +08:00
[FeatureR600, FeatureWavefrontSize64, FeatureVertexCache]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
//===----------------------------------------------------------------------===//
// Radeon HD 4000 Series (R700).
//===----------------------------------------------------------------------===//
def : Processor<"rv710", R600_VLIW5_Itin,
[FeatureR700, FeatureWavefrontSize32, FeatureVertexCache]
>;
def : Processor<"rv730", R600_VLIW5_Itin,
[FeatureR700, FeatureWavefrontSize32, FeatureVertexCache]
>;
def : Processor<"rv770", R600_VLIW5_Itin,
AMDGPU: Disable fp64 support on pre GCN asics It's not implemented. Passing +fp64-fp16-denormal feature enables fp64 even on asics that don't support it v2: fix hasFP64 query Differential Revision: https://reviews.llvm.org/D39931 llvm-svn: 319709
2017-12-05 06:57:29 +08:00
[FeatureR700, FeatureWavefrontSize64, FeatureVertexCache]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
//===----------------------------------------------------------------------===//
// Radeon HD 5000 Series (Evergreen).
//===----------------------------------------------------------------------===//
def : Processor<"cedar", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize32, FeatureVertexCache,
FeatureCFALUBug]
>;
def : Processor<"cypress", R600_VLIW5_Itin,
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction Only used by pre-GCN targets v2: fix predicate setting for FMA_Common Differential Revision: https://reviews.llvm.org/D40692 llvm-svn: 319712
2017-12-05 07:07:28 +08:00
[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache, FeatureFMA]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
def : Processor<"juniper", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache]
>;
def : Processor<"redwood", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache,
FeatureCFALUBug]
>;
def : Processor<"sumo", R600_VLIW5_Itin,
[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]
>;
//===----------------------------------------------------------------------===//
// Radeon HD 6000 Series (Northern Islands).
//===----------------------------------------------------------------------===//
def : Processor<"barts", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
>;
def : Processor<"caicos", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureCFALUBug]
>;
def : Processor<"cayman", R600_VLIW4_Itin,
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction Only used by pre-GCN targets v2: fix predicate setting for FMA_Common Differential Revision: https://reviews.llvm.org/D40692 llvm-svn: 319712
2017-12-05 07:07:28 +08:00
[FeatureNorthernIslands, FeatureCaymanISA, FeatureFMA]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td Differential Revision: https://reviews.llvm.org/D39880 llvm-svn: 317920
2017-11-11 04:01:58 +08:00
>;
def : Processor<"turks", R600_VLIW5_Itin,
[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
>;