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llvm-project/llvm/test/MC/Mips/mips64-expansions.s

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[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -mcpu=mips64r2 -mattr=-xgot \
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# RUN: -show-encoding | FileCheck --check-prefixes=CHECK,GOT %s
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -mcpu=mips64r2 -mattr=+xgot \
# RUN: -show-encoding | FileCheck --check-prefixes=CHECK,XGOT %s
[mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI. Summary: To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI. This currently happens because of sign extension. To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8662 llvm-svn: 237428
2015-05-15 17:42:11 +08:00
# Check that signed negative 32-bit immediates are loaded correctly:
li $10, ~(0x101010)
# CHECK: lui $10, 65519 # encoding: [0xef,0xff,0x0a,0x3c]
# CHECK: ori $10, $10, 61423 # encoding: [0xef,0xef,0x4a,0x35]
# CHECK-NOT: dsll
Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
2015-06-11 18:36:10 +08:00
# Test bne with an immediate as the 2nd operand.
bne $2, 0x100010001, 1332
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
2015-06-11 18:36:10 +08:00
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
bne $2, 0x1000100010001, 1332
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
bne $2, -0x100010001, 1332
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, -2 # encoding: [0xfe,0xff,0x01,0x24]
Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
2015-06-11 18:36:10 +08:00
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
bne $2, -0x1000100010001, 1332
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: bne $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x14]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# Test beq with an immediate as the 2nd operand.
beq $2, 0x100010001, 1332
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
2015-06-11 18:36:10 +08:00
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
beq $2, 0x1000100010001, 1332
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
beq $2, -0x100010001, 1332
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, -2 # encoding: [0xfe,0xff,0x01,0x24]
Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
2015-06-11 18:36:10 +08:00
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
beq $2, -0x1000100010001, 1332
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
[mips] Make symbols an acceptable branch target when expanding compare-to-immediate-and-branch macros. Reviewers: vkalintiris Subscribers: llvm-commits, vkalintiris, dim, seanbruno, dsanders Differential Revision: http://reviews.llvm.org/D15369 llvm-svn: 262213
2016-02-29 19:24:49 +08:00
# Test one with a symbol in the third operand.
sym:
bne $2, 0x100010001, sym
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: bne $2, $1, sym # encoding: [A,A,0x41,0x14]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
# Test ulhu with 64-bit immediate addresses.
ulhu $8, 0x100010001
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulhu $8, 0x1000100010001
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulhu $8, -0x100010001
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, -2 # encoding: [0xfe,0xff,0x01,0x24]
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulhu $8, -0x1000100010001
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
# Test ulhu with source register and 64-bit immediate offset.
ulhu $8, 0x100010001($9)
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulhu $8, 0x1000100010001($9)
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulhu $8, -0x100010001($9)
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, -2 # encoding: [0xfe,0xff,0x01,0x24]
[mips] [IAS] Add partial support for the ULHU pseudo-instruction. Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
2015-06-23 22:39:42 +08:00
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulhu $8, -0x1000100010001($9)
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lbu $8, 1($1) # encoding: [0x01,0x00,0x28,0x90]
# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
[mips] [IAS] Add partial support for the ULW pseudo-instruction. Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
2015-06-26 21:20:17 +08:00
# Test ulw with 64-bit immediate addresses.
ulw $8, 0x100010001
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
[mips] [IAS] Add partial support for the ULW pseudo-instruction. Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
2015-06-26 21:20:17 +08:00
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
ulw $8, 0x1000100010001
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
ulw $8, -0x100010001
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, -2 # encoding: [0xfe,0xff,0x01,0x24]
[mips] [IAS] Add partial support for the ULW pseudo-instruction. Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
2015-06-26 21:20:17 +08:00
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
ulw $8, -0x1000100010001
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
# Test ulw with source register and 64-bit immediate offset.
ulw $8, 0x100010001($9)
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
[mips] [IAS] Add partial support for the ULW pseudo-instruction. Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
2015-06-26 21:20:17 +08:00
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
ulw $8, 0x1000100010001($9)
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
ulw $8, -0x100010001($9)
[mips] [IAS] Add support for the DLA pseudo-instruction and fix problems with DLI Summary: It is the same as LA, except that it can also load 64-bit addresses and it only works on 64-bit MIPS architectures. Reviewers: tomatabacu, seanbruno, vkalintiris Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9524 llvm-svn: 245208
2015-08-17 18:11:55 +08:00
# CHECK: addiu $1, $zero, -2 # encoding: [0xfe,0xff,0x01,0x24]
[mips] [IAS] Add partial support for the ULW pseudo-instruction. Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
2015-06-26 21:20:17 +08:00
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
ulw $8, -0x1000100010001($9)
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
[mips] Accept 32-bit offsets for ld/sd/lld commands This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
2018-05-11 00:01:36 +08:00
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
2018-06-02 00:37:53 +08:00
# Test lb/sb/ld/sd/lld with offsets exceeding 16-bits in size.
[mips] Accept 32-bit offsets for ld/sd/lld commands This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
2018-05-11 00:01:36 +08:00
ld $4, 0x8000
# CHECK: lui $4, 1
# CHECK-NEXT: ld $4, -32768($4)
ld $4, 0x20008($3)
# CHECK: lui $4, 2
# CHECK-NEXT: addu $4, $4, $3
# CHECK-NEXT: ld $4, 8($4)
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
2018-06-02 00:37:53 +08:00
ld $4,0x100010004
# CHECK: addiu $4, $zero, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ld $4, 4($4)
ld $4,0x1800180018004
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ld $4, -32764($4)
ld $4,0x1800180018004($3)
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: daddu $4, $4, $3
# CHECK-NEXT: ld $4, -32764($4)
[mips] Accept 32-bit offsets for ld/sd/lld commands This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
2018-05-11 00:01:36 +08:00
sd $4, 0x8000
# CHECK: lui $1, 1
# CHECK-NEXT: sd $4, -32768($1)
sd $4, 0x20008($3)
# CHECK: lui $1, 2
# CHECK-NEXT: addu $1, $1, $3
# CHECK-NEXT: sd $4, 8($1)
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
2018-06-02 00:37:53 +08:00
sd $4,0x100010004
# CHECK: addiu $1, $zero, 1
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: ori $1, $1, 1
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: sd $4, 4($1)
sd $4,0x1800180018004
# CHECK: lui $1, 1
# CHECK-NEXT: ori $1, $1, 32769
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: ori $1, $1, 32770
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: sd $4, -32764($1)
sd $4,0x1800180018004($3)
# CHECK: lui $1, 1
# CHECK-NEXT: ori $1, $1, 32769
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: ori $1, $1, 32770
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: daddu $1, $1, $3
# CHECK-NEXT: sd $4, -32764($1)
[mips] Accept 32-bit offsets for ld/sd/lld commands This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
2018-05-11 00:01:36 +08:00
lld $4, 0x8000
# CHECK: lui $4, 1
# CHECK-NEXT: lld $4, -32768($4)
lld $4, 0x20008($3)
# CHECK: lui $4, 2
# CHECK-NEXT: addu $4, $4, $3
# CHECK-NEXT: lld $4, 8($4)
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
2018-06-02 00:37:53 +08:00
lld $4,0x100010004
# CHECK: addiu $4, $zero, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lld $4, 4($4)
lld $4,0x1800180018004
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lld $4, -32764($4)
lld $4,0x1800180018004($3)
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: daddu $4, $4, $3
# CHECK-NEXT: lld $4, -32764($4)
lb $4,0x100010004
# CHECK: addiu $4, $zero, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lb $4, 4($4)
lb $4,0x1800180018004
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lb $4, -32764($4)
lb $4,0x1800180018004($3)
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: daddu $4, $4, $3
# CHECK-NEXT: lb $4, -32764($4)
sb $4,0x100010004
# CHECK: addiu $1, $zero, 1
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: ori $1, $1, 1
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: sb $4, 4($1)
sb $4,0x1800180018004
# CHECK: lui $1, 1
# CHECK-NEXT: ori $1, $1, 32769
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: ori $1, $1, 32770
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: sb $4, -32764($1)
sb $4,0x1800180018004($3)
# CHECK: lui $1, 1
# CHECK-NEXT: ori $1, $1, 32769
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: ori $1, $1, 32770
# CHECK-NEXT: dsll $1, $1, 16
# CHECK-NEXT: daddu $1, $1, $3
# CHECK-NEXT: sb $4, -32764($1)
lh $4,0x100010004
# CHECK: addiu $4, $zero, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lh $4, 4($4)
lh $4,0x1800180018004
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lh $4, -32764($4)
lh $4,0x1800180018004($3)
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: daddu $4, $4, $3
# CHECK-NEXT: lh $4, -32764($4)
lhu $4,0x100010004
# CHECK: addiu $4, $zero, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 1
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lhu $4, 4($4)
lhu $4,0x1800180018004
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: lhu $4, -32764($4)
lhu $4,0x1800180018004($3)
# CHECK: lui $4, 1
# CHECK-NEXT: ori $4, $4, 32769
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: ori $4, $4, 32770
# CHECK-NEXT: dsll $4, $4, 16
# CHECK-NEXT: daddu $4, $4, $3
# CHECK-NEXT: lhu $4, -32764($4)
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
# LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
.option pic2
lw $10, symbol($4)
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $10, %got_disp(symbol)($gp) # encoding: [A,A,0x8a,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: daddu $10, $10, $4 # encoding: [0x2d,0x50,0x44,0x01]
# GOT-NEXT: lw $10, 0($10) # encoding: [0x00,0x00,0x4a,0x8d]
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $10, %got_hi(symbol) # encoding: [A,A,0x0a,0x3c]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_hi(symbol), kind: fixup_Mips_GOT_HI16
# XGOT-NEXT: daddu $10, $10, $gp # encoding: [0x2d,0x50,0x5c,0x01]
# XGOT-NEXT: ld $10, %got_lo(symbol)($10) # encoding: [A,A,0x4a,0xdd]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_lo(symbol), kind: fixup_Mips_GOT_LO16
# XGOT-NEXT: daddu $10, $10, $4 # encoding: [0x2d,0x50,0x44,0x01]
# XGOT-NEXT: lw $10, 0($10) # encoding: [0x00,0x00,0x4a,0x8d]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
sw $10, symbol($9)
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $1, %got_disp(symbol)($gp) # encoding: [A,A,0x81,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# GOT-NEXT: sw $10, 0($1) # encoding: [0x00,0x00,0x2a,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $1, %got_hi(symbol) # encoding: [A,A,0x01,0x3c]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_hi(symbol), kind: fixup_Mips_GOT_HI16
# XGOT-NEXT: daddu $1, $1, $gp # encoding: [0x2d,0x08,0x3c,0x00]
# XGOT-NEXT: ld $1, %got_lo(symbol)($1) # encoding: [A,A,0x21,0xdc]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_lo(symbol), kind: fixup_Mips_GOT_LO16
# XGOT-NEXT: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# XGOT-NEXT: sw $10, 0($1) # encoding: [0x00,0x00,0x2a,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
lw $8, sym+8
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $8, %got_disp(sym)($gp) # encoding: [A,A,0x88,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(sym), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: lw $8, 8($8) # encoding: [0x08,0x00,0x08,0x8d]
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: ld $8, %got_disp(sym)($gp) # encoding: [A,A,0x88,0xdf]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_disp(sym), kind: fixup_Mips_GOT_DISP
# XGOT-NEXT: lw $8, 8($8) # encoding: [0x08,0x00,0x08,0x8d]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
sw $8, sym+8
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $1, %got_disp(sym)($gp) # encoding: [A,A,0x81,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(sym), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: sw $8, 8($1) # encoding: [0x08,0x00,0x28,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: ld $1, %got_disp(sym)($gp) # encoding: [A,A,0x81,0xdf]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_disp(sym), kind: fixup_Mips_GOT_DISP
# XGOT-NEXT: sw $8, 8($1) # encoding: [0x08,0x00,0x28,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
lw $10, 655483($4)
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: lui $10, 10 # encoding: [0x0a,0x00,0x0a,0x3c]
# GOT-NEXT: daddu $10, $10, $4 # encoding: [0x2d,0x50,0x44,0x01]
# GOT-NEXT: lw $10, 123($10) # encoding: [0x7b,0x00,0x4a,0x8d]
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $10, 10 # encoding: [0x0a,0x00,0x0a,0x3c]
# XGOT-NEXT: daddu $10, $10, $4 # encoding: [0x2d,0x50,0x44,0x01]
# XGOT-NEXT: lw $10, 123($10) # encoding: [0x7b,0x00,0x4a,0x8d]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
sw $10, 123456($9)
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: lui $1, 2 # encoding: [0x02,0x00,0x01,0x3c]
# GOT-NEXT: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# GOT-NEXT: sw $10, -7616($1) # encoding: [0x40,0xe2,0x2a,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $1, 2 # encoding: [0x02,0x00,0x01,0x3c]
# XGOT-NEXT: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
# XGOT-NEXT: sw $10, -7616($1) # encoding: [0x40,0xe2,0x2a,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
lw $8, symbol+8
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $8, %got_disp(symbol)($gp) # encoding: [A,A,0x88,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: lw $8, 8($8) # encoding: [0x08,0x00,0x08,0x8d]
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $8, %got_hi(symbol) # encoding: [A,A,0x08,0x3c]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_hi(symbol), kind: fixup_Mips_GOT_HI16
# XGOT-NEXT: daddu $8, $8, $gp # encoding: [0x2d,0x40,0x1c,0x01]
# XGOT-NEXT: ld $8, %got_lo(symbol)($8) # encoding: [A,A,0x08,0xdd]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_lo(symbol), kind: fixup_Mips_GOT_LO16
# XGOT-NEXT: lw $8, 8($8) # encoding: [0x08,0x00,0x08,0x8d]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
sw $8, symbol+8
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $1, %got_disp(symbol)($gp) # encoding: [A,A,0x81,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: sw $8, 8($1) # encoding: [0x08,0x00,0x28,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $1, %got_hi(symbol) # encoding: [A,A,0x01,0x3c]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_hi(symbol), kind: fixup_Mips_GOT_HI16
# XGOT-NEXT: daddu $1, $1, $gp # encoding: [0x2d,0x08,0x3c,0x00]
# XGOT-NEXT: ld $1, %got_lo(symbol)($1) # encoding: [A,A,0x21,0xdc]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_lo(symbol), kind: fixup_Mips_GOT_LO16
# XGOT-NEXT: sw $8, 8($1) # encoding: [0x08,0x00,0x28,0xac]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
ldc1 $f0, symbol
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $1, %got_disp(symbol)($gp) # encoding: [A,A,0x81,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: ldc1 $f0, 0($1) # encoding: [0x00,0x00,0x20,0xd4]
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $1, %got_hi(symbol) # encoding: [A,A,0x01,0x3c]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_hi(symbol), kind: fixup_Mips_GOT_HI16
# XGOT-NEXT: daddu $1, $1, $gp # encoding: [0x2d,0x08,0x3c,0x00]
# XGOT-NEXT: ld $1, %got_lo(symbol)($1) # encoding: [A,A,0x21,0xdc]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_lo(symbol), kind: fixup_Mips_GOT_LO16
# XGOT-NEXT: ldc1 $f0, 0($1) # encoding: [0x00,0x00,0x20,0xd4]
[mips] Fix lowering load/store instruction in PIC case If an operand of the `lw/sw` instructions is a symbol, these instructions incorrectly lowered using not-position-independent chain of commands. For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16` and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16` relocations. This patch provides a fix for the bug by handling PIC case separately in the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain of PIC instructions to load a symbol address into a register and then load the address content. The fix is not optimal and does not fix all PIC-related problems. This is a task for subsequent patches. Differential Revision: https://reviews.llvm.org/D65524 llvm-svn: 367580
2019-08-02 00:04:29 +08:00
sdc1 $f0, symbol
[mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFC That simplify adding XGOT tests later. llvm-svn: 372219
2019-09-18 20:24:30 +08:00
# GOT: ld $1, %got_disp(symbol)($gp) # encoding: [A,A,0x81,0xdf]
# GOT-NEXT: # fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
# GOT-NEXT: sdc1 $f0, 0($1) # encoding: [0x00,0x00,0x20,0xf4]
[mips] Expand 'lw/sw' instructions for 32-bit GOT In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
2019-09-19 03:19:47 +08:00
# XGOT: lui $1, %got_hi(symbol) # encoding: [A,A,0x01,0x3c]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_hi(symbol), kind: fixup_Mips_GOT_HI16
# XGOT-NEXT: daddu $1, $1, $gp # encoding: [0x2d,0x08,0x3c,0x00]
# XGOT-NEXT: ld $1, %got_lo(symbol)($1) # encoding: [A,A,0x21,0xdc]
# XGOT-NEXT: # fixup A - offset: 0, value: %got_lo(symbol), kind: fixup_Mips_GOT_LO16
# XGOT-NEXT: sdc1 $f0, 0($1) # encoding: [0x00,0x00,0x20,0xf4]