llvm-project/llvm/test/MC/Hexagon/iconst.s

# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s

a:
# CHECK: r0 = add(r0,#0)
# CHECK: R_HEX_27_REG
r0 = iconst(#a)
Revert r265817 lld tests need to be addressed. llvm-svn: 265822 2016-04-09 02:15:37 +08:00			`# RUN: llvm-mc -triple=hexagon -filetype=obj %s \| llvm-objdump -d -r - \| FileCheck %s`
[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding. The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes. Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware. This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register. llvm-svn: 261006 2016-02-17 04:38:17 +08:00
			`a:`
[Hexagon] Replace instruction definitions with auto-generated ones llvm-svn: 294753 2017-02-10 23:33:13 +08:00			`# CHECK: r0 = add(r0,#0)`
[Hexagon] Change iconst to emit 27bit relocation Patch by Colin LeMahieu. llvm-svn: 301956 2017-05-03 02:19:11 +08:00			`# CHECK: R_HEX_27_REG`
[Hexagon] Replace instruction definitions with auto-generated ones llvm-svn: 294753 2017-02-10 23:33:13 +08:00			`r0 = iconst(#a)`