maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/AVR/inst-lds.s

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

26 lines
915 B
ArmAsm
Raw Normal View History

[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s
[AVR] Implement disassembly of 32-bit instructions This needed two fixes: * 32-bit instructions were read in the wrong order. The machine code swaps the two 16-bit instruction words, which wasn't undone when decoding instructions. * Jump and call instructions don't encode the lowest address bit, which is always zero. Therefore, the address needed to be shifted by one to fix that. Differential Revision: https://reviews.llvm.org/D81961
2020-06-17 03:39:09 +08:00
; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -dr --mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
foo:
lds r16, 241
lds r29, 190
lds r22, 172
lds r27, 92
lds r4, SYMBOL+12
; CHECK: lds r16, 241 ; encoding: [0x00,0x91,0xf1,0x00]
; CHECK: lds r29, 190 ; encoding: [0xd0,0x91,0xbe,0x00]
; CHECK: lds r22, 172 ; encoding: [0x60,0x91,0xac,0x00]
; CHECK: lds r27, 92 ; encoding: [0xb0,0x91,0x5c,0x00]
[AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offset Before this, the LDS/STS instructions would have their opcodes overwritten while linking. llvm-svn: 301782
2017-05-01 07:33:52 +08:00
; CHECK: lds r4, SYMBOL+12 ; encoding: [0x40,0x90,A,A]
; CHECK: ; fixup A - offset: 2, value: SYMBOL+12, kind: fixup_16
[AVR] Implement disassembly of 32-bit instructions This needed two fixes: * 32-bit instructions were read in the wrong order. The machine code swaps the two 16-bit instruction words, which wasn't undone when decoding instructions. * Jump and call instructions don't encode the lowest address bit, which is always zero. Therefore, the address needed to be shifted by one to fix that. Differential Revision: https://reviews.llvm.org/D81961
2020-06-17 03:39:09 +08:00
; CHECK-INST: lds r16, 241
; CHECK-INST: lds r29, 190
; CHECK-INST: lds r22, 172
; CHECK-INST: lds r27, 92
; CHECK-INST: lds r4, 0
; CHECK-INST: R_AVR_16 SYMBOL+0xc