maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/PowerPC/PPC.td

107 lines
4.9 KiB
TableGen
Raw Normal View History

Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
//
//===----------------------------------------------------------------------===//
//
// This is the top level entry point for the PowerPC target.
//
//===----------------------------------------------------------------------===//
// Get the target-independent interfaces which we are implementing.
//
Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. llvm-svn: 59953
2008-11-24 15:34:46 +08:00
include "llvm/Target/Target.td"
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//===----------------------------------------------------------------------===//
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
// PowerPC Subtarget features.
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//
Honor cpu directive, take two. llvm-svn: 32492
2006-12-13 04:57:08 +08:00
//===----------------------------------------------------------------------===//
// CPU Directives //
//===----------------------------------------------------------------------===//
def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
Rename some subtarget features. A CPU now can *have* 64-bit instructions, can in 32-bit mode we can choose to optionally *use* 64-bit registers. llvm-svn: 28824
2006-06-17 01:34:12 +08:00
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
improve -help output llvm-svn: 23892
2005-10-23 13:28:51 +08:00
"Enable 64-bit instructions">;
Rename some subtarget features. A CPU now can *have* 64-bit instructions, can in 32-bit mode we can choose to optionally *use* 64-bit registers. llvm-svn: 28824
2006-06-17 01:34:12 +08:00
def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
"Enable 64-bit registers usage for ppc32 [beta]">;
Subtarget feature can now set any variable to any value llvm-svn: 25678
2006-01-27 16:09:42 +08:00
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
improve -help output llvm-svn: 23892
2005-10-23 13:28:51 +08:00
"Enable Altivec instructions">;
Subtarget feature can now set any variable to any value llvm-svn: 25678
2006-01-27 16:09:42 +08:00
def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
improve -help output llvm-svn: 23892
2005-10-23 13:28:51 +08:00
"Enable GPUL instructions">;
Subtarget feature can now set any variable to any value llvm-svn: 25678
2006-01-27 16:09:42 +08:00
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
improve -help output llvm-svn: 23892
2005-10-23 13:28:51 +08:00
"Enable the fsqrt instruction">;
Add a subtarget feature for the stfiwx instruction. I know the G5 has it, but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) llvm-svn: 26421
2006-02-28 15:08:22 +08:00
def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
"Enable the stfiwx instruction">;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//===----------------------------------------------------------------------===//
rearrange things a bit so that instructions can use subtarget features in the future. llvm-svn: 23902
2005-10-24 06:08:13 +08:00
// Register File Description
//===----------------------------------------------------------------------===//
include "PPCRegisterInfo.td"
include "PPCSchedule.td"
include "PPCInstrInfo.td"
//===----------------------------------------------------------------------===//
// PowerPC processors supported.
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//
Honor cpu directive, take two. llvm-svn: 32492
2006-12-13 04:57:08 +08:00
def : Processor<"generic", G3Itineraries, [Directive32]>;
def : Processor<"601", G3Itineraries, [Directive601]>;
def : Processor<"602", G3Itineraries, [Directive602]>;
def : Processor<"603", G3Itineraries, [Directive603]>;
def : Processor<"603e", G3Itineraries, [Directive603]>;
def : Processor<"603ev", G3Itineraries, [Directive603]>;
def : Processor<"604", G3Itineraries, [Directive604]>;
def : Processor<"604e", G3Itineraries, [Directive604]>;
def : Processor<"620", G3Itineraries, [Directive620]>;
def : Processor<"g3", G3Itineraries, [Directive7400]>;
def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"970", G5Itineraries,
Honor cpu directive, take two. llvm-svn: 32492
2006-12-13 04:57:08 +08:00
[Directive970, FeatureAltivec,
FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
Feature64Bit /*, Feature64BitRegs */]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"g5", G5Itineraries,
Honor cpu directive, take two. llvm-svn: 32492
2006-12-13 04:57:08 +08:00
[Directive970, FeatureAltivec,
FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"ppc", G3Itineraries, [Directive32]>;
def : Processor<"ppc64", G5Itineraries,
[Directive64, FeatureAltivec,
FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
Feature64Bit /*, Feature64BitRegs */]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
Switch PPC return lower to use an autogenerated CC description. llvm-svn: 34940
2007-03-06 08:59:59 +08:00
//===----------------------------------------------------------------------===//
// Calling Conventions
//===----------------------------------------------------------------------===//
include "PPCCallingConv.td"
Several big changes: 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
2006-03-12 17:13:49 +08:00
def PPCInstrInfo : InstrInfo {
let isLittleEndianEncoding = 1;
}
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
def PPC : Target {
Several big changes: 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. llvm-svn: 26719
2006-03-12 17:13:49 +08:00
// Information about the instructions.
let InstructionSet = PPCInstrInfo;
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
}