2012-09-22 08:06:06 +08:00
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//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def HasDSP : Predicate<"Subtarget.hasDSP()">,
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AssemblerPredicate<"FeatureDSP">;
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def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
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AssemblerPredicate<"FeatureDSPR2">;
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// Fields.
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class Field6<bits<6> val> {
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bits<6> V = val;
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}
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def SPECIAL3_OPCODE : Field6<0b011111>;
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def REGIMM_OPCODE : Field6<0b000001>;
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class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasDSP];
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}
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2012-09-27 10:05:42 +08:00
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// EXTR.W sub-class format (type 1).
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class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
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bits<5> rt;
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bits<2> ac;
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bits<5> shift_rs;
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let Opcode = SPECIAL3_OPCODE.V;
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let Inst{25-21} = shift_rs;
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let Inst{20-16} = rt;
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let Inst{15-13} = 0;
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let Inst{12-11} = ac;
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let Inst{10-6} = op;
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let Inst{5-0} = 0b111000;
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}
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