2017-06-20 06:43:19 +08:00
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//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
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2005-07-12 09:41:54 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-07-12 09:41:54 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2016-11-23 06:09:03 +08:00
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/// \file This file describes the general parts of a Subtarget.
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2005-07-12 09:41:54 +08:00
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//
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//===----------------------------------------------------------------------===//
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2017-06-20 06:43:19 +08:00
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#include "llvm/ADT/Optional.h"
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2017-04-14 15:44:23 +08:00
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#include "llvm/CodeGen/MachineInstr.h"
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2017-11-08 09:01:31 +08:00
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#include "llvm/CodeGen/TargetInstrInfo.h"
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2017-04-14 15:44:23 +08:00
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#include "llvm/CodeGen/TargetSchedule.h"
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2017-06-20 06:43:19 +08:00
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/Format.h"
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2017-04-14 15:44:23 +08:00
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#include "llvm/Support/raw_ostream.h"
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2017-06-20 06:43:19 +08:00
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#include <string>
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2005-07-12 09:41:54 +08:00
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using namespace llvm;
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2015-07-11 06:43:42 +08:00
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TargetSubtargetInfo::TargetSubtargetInfo(
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2015-09-16 00:17:27 +08:00
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const Triple &TT, StringRef CPU, StringRef FS,
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2015-07-11 06:43:42 +08:00
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ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
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const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
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}
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2005-07-12 09:41:54 +08:00
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2017-06-20 06:43:19 +08:00
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TargetSubtargetInfo::~TargetSubtargetInfo() = default;
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2009-11-10 08:48:55 +08:00
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2014-08-22 05:50:01 +08:00
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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2014-06-20 05:03:04 +08:00
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return true;
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}
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Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
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bool TargetSubtargetInfo::enableIndirectBrExpand() const {
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return false;
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}
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2012-11-13 16:47:29 +08:00
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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2015-03-12 06:56:10 +08:00
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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return enableMachineScheduler();
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}
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2014-07-03 02:32:04 +08:00
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOpt::Level OptLevel) const {
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return true;
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}
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Add logic to greedy reg alloc to avoid bad eviction chains
This fixes bugzilla 26810
https://bugs.llvm.org/show_bug.cgi?id=26810
This is intended to prevent sequences like:
movl %ebp, 8(%esp) # 4-byte Spill
movl %ecx, %ebp
movl %ebx, %ecx
movl %edi, %ebx
movl %edx, %edi
cltd
idivl %esi
movl %edi, %edx
movl %ebx, %edi
movl %ecx, %ebx
movl %ebp, %ecx
movl 16(%esp), %ebp # 4 - byte Reload
Such sequences are created in 2 scenarios:
Scenario #1:
vreg0 is evicted from physreg0 by vreg1
Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from)
Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.)
one of the split intervals ends up evicting vreg2 from physreg1
Evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
Scenario #2
vreg0 is evicted from physreg0 by vreg1
vreg2 is evicted from physreg2 by vreg3 etc
Evictee vreg0 is intended for region splitting with split candidate physreg1
Region splitting creates a local interval because of interference with the evictor vreg1
one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from)
Another evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest).
Differential Revision: https://reviews.llvm.org/D35816
Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39
llvm-svn: 316295
2017-10-23 01:59:38 +08:00
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bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
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return false;
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}
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2015-06-13 11:42:16 +08:00
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bool TargetSubtargetInfo::enablePostRAScheduler() const {
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2014-09-03 01:43:54 +08:00
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return getSchedModel().PostRAScheduler;
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2009-11-10 08:48:55 +08:00
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}
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2013-08-29 11:25:05 +08:00
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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2017-04-14 15:44:23 +08:00
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static std::string createSchedInfoStr(unsigned Latency,
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2018-03-14 23:28:48 +08:00
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Optional<double> RThroughput) {
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2017-04-14 15:44:23 +08:00
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static const char *SchedPrefix = " sched: [";
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std::string Comment;
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raw_string_ostream CS(Comment);
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2018-03-14 23:28:48 +08:00
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if (RThroughput.hasValue())
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CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
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<< "]";
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2018-03-14 23:28:48 +08:00
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else
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CS << SchedPrefix << Latency << ":?]";
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CS.flush();
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return Comment;
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}
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/// Returns string representation of scheduler comment
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std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
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if (MI.isPseudo() || MI.isTerminator())
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return std::string();
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// We don't cache TSchedModel because it depends on TargetInstrInfo
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// that could be changed during the compilation
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TargetSchedModel TSchedModel;
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TSchedModel.init(getSchedModel(), this, getInstrInfo());
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unsigned Latency = TSchedModel.computeInstrLatency(&MI);
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Optional<double> RThroughput = TSchedModel.computeInstrRThroughput(&MI);
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return createSchedInfoStr(Latency, RThroughput);
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}
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/// Returns string representation of scheduler comment
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std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
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// We don't cache TSchedModel because it depends on TargetInstrInfo
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// that could be changed during the compilation
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TargetSchedModel TSchedModel;
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TSchedModel.init(getSchedModel(), this, getInstrInfo());
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2017-08-01 17:15:43 +08:00
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unsigned Latency;
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if (TSchedModel.hasInstrSchedModel())
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Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
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else if (TSchedModel.hasInstrItineraries()) {
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auto *ItinData = TSchedModel.getInstrItineraries();
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Latency = ItinData->getStageLatency(
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getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
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} else
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2017-04-14 15:44:23 +08:00
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return std::string();
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Optional<double> RThroughput =
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TSchedModel.computeInstrRThroughput(MCI.getOpcode());
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return createSchedInfoStr(Latency, RThroughput);
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}
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2018-01-19 11:16:36 +08:00
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void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
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}
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