2012-05-05 04:18:50 +08:00
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//===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the NVPTX target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "nvptx-isel"
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#include "NVPTX.h"
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#include "NVPTXISelLowering.h"
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#include "NVPTXRegisterInfo.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/Intrinsics.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Support/Compiler.h"
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2012-05-05 04:18:50 +08:00
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using namespace llvm;
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namespace {
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class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
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// If true, generate corresponding FPCONTRACT. This is
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// language dependent (i.e. CUDA and OpenCL works differently).
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bool doFMADF32;
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bool doFMAF64;
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bool doFMAF32;
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bool doFMAF64AGG;
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bool doFMAF32AGG;
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bool allowFMA;
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// 0: use div.approx
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// 1: use div.full
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// 2: For sm_20 and later, ieee-compliant div.rnd.f32 can be generated;
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// Otherwise, use div.full
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int do_DIVF32_PREC;
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2013-05-22 00:51:30 +08:00
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// If true, generate sqrt.rn, else generate sqrt.approx. If FTZ
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// is true, then generate the corresponding FTZ version.
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bool do_SQRTF32_PREC;
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2012-05-05 04:18:50 +08:00
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// If true, add .ftz to f32 instructions.
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// This is only meaningful for sm_20 and later, as the default
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// is not ftz.
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// For sm earlier than sm_20, f32 denorms are always ftz by the
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// hardware.
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// We always add the .ftz modifier regardless of the sm value
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// when Use32FTZ is true.
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bool UseF32FTZ;
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// If true, generate mul.wide from sext and mul
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bool doMulWide;
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public:
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explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
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CodeGenOpt::Level OptLevel);
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// Pass Name
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virtual const char *getPassName() const {
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return "NVPTX DAG->DAG Pattern Instruction Selection";
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}
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const NVPTXSubtarget &Subtarget;
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2013-03-30 22:29:21 +08:00
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virtual bool SelectInlineAsmMemoryOperand(
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const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps);
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2012-05-05 04:18:50 +08:00
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private:
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2013-03-30 22:29:21 +08:00
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// Include the pieces autogenerated from the target description.
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2012-05-05 04:18:50 +08:00
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#include "NVPTXGenDAGISel.inc"
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SDNode *Select(SDNode *N);
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2013-02-12 22:18:49 +08:00
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SDNode *SelectLoad(SDNode *N);
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SDNode *SelectLoadVector(SDNode *N);
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SDNode *SelectLDGLDUVector(SDNode *N);
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SDNode *SelectStore(SDNode *N);
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SDNode *SelectStoreVector(SDNode *N);
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2013-06-29 01:57:59 +08:00
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SDNode *SelectLoadParam(SDNode *N);
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SDNode *SelectStoreRetval(SDNode *N);
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SDNode *SelectStoreParam(SDNode *N);
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2012-05-05 04:18:50 +08:00
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inline SDValue getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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// Match direct address complex pattern.
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bool SelectDirectAddr(SDValue N, SDValue &Address);
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bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
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SDValue &Offset, MVT mvt);
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bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
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SDValue &Offset);
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bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
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SDValue &Offset);
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bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
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SDValue &Offset, MVT mvt);
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bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
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SDValue &Offset);
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bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
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SDValue &Offset);
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bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
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bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);
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};
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}
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