2017-12-03 06:13:22 +08:00
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; RUN: llc -debug-only=machine-scheduler -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s
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target datalayout = "A5"
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2016-09-23 01:28:43 +08:00
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; REQUIRES: asserts
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; Verify that the extload generated from %eval has the default
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; alignment size (2) corresponding to the underlying memory size (i16)
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; size and not 4 corresponding to the sign-extended size (i32).
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; DEBUG: {{^}}# Machine code for function extload_align:
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2018-01-09 23:39:44 +08:00
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; DEBUG: mem:LD2[<unknown>(addrspace=5)]
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2016-09-23 01:28:43 +08:00
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; DEBUG: {{^}}# End machine code for function extload_align.
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2017-12-03 06:13:22 +08:00
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define amdgpu_kernel void @extload_align(i32 addrspace(5)* %out, i32 %index) #0 {
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%v0 = alloca [4 x i16], addrspace(5)
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%a1 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 0
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%a2 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 1
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store i16 0, i16 addrspace(5)* %a1
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store i16 1, i16 addrspace(5)* %a2
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%a = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 %index
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%val = load i16, i16 addrspace(5)* %a
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2016-09-23 01:28:43 +08:00
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%eval = sext i16 %val to i32
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2017-12-03 06:13:22 +08:00
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store i32 %eval, i32 addrspace(5)* %out
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2016-09-23 01:28:43 +08:00
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ret void
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2017-05-26 05:26:32 +08:00
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}
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