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llvm-project/llvm/test/CodeGen/PowerPC/ori_imm32.ll

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[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
[PowerPC] [NFC] Add AIX triple to some regression tests As part of the effort to improve AIX support, regression test coverage misses quite a lot for AIX subtarget. This patch adds AIX triple to those don't need extra change, and we can cover more cases in following commits. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D94159
2021-01-18 11:44:00 +08:00
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
define i64 @ori_test_a(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: ori_test_a:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori 3, 3, 65535
; CHECK-NEXT: oris 3, 3, 65535
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%or = or i64 %a, 4294967295
ret i64 %or
}
define i64 @ori_test_b(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: ori_test_b:
; CHECK: # %bb.0: # %entry
[PowerPC] Exploit RLDIMI for OR with large immediates This patch exploits rldimi instruction for patterns like `or %a, 0b000011110000`, which saves number of instructions when the operand has only one use, compared with `li-ori-sldi-or`. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D77850
2020-04-17 15:08:58 +08:00
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldimi 3, 4, 32, 31
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%or = or i64 %a, 4294967296
ret i64 %or
}
define i64 @ori_test_c(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: ori_test_c:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori 3, 3, 65535
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%or = or i64 %a, 65535
ret i64 %or
}
define i64 @ori_test_d(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: ori_test_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: oris 3, 3, 1
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%or = or i64 %a, 65536
ret i64 %or
}
define zeroext i32 @ori_test_e(i32 zeroext %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: ori_test_e:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ori 3, 3, 65535
; CHECK-NEXT: oris 3, 3, 255
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%or = or i32 %a, 16777215
ret i32 %or
}
define i64 @xori_test_a(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: xori_test_a:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xori 3, 3, 65535
; CHECK-NEXT: xoris 3, 3, 65535
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%xor = xor i64 %a, 4294967295
ret i64 %xor
}
define i64 @xori_test_b(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: xori_test_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, 1
[PowerPC] Materialize i64 constants by enumerated patterns. Summary: Some constants can be handled with less instructions than our current results. And it seems our original approach is not very easy to extend. Therefore this patch proposes to materialize all 64-bit constants by enumerated patterns. I traversed almost all constants to verified the functionality of these pattens. A traversed comparison of the number of instructions used by the original method and the new method has also been completed, where no degradation was caused by this patch. This patch also passed Bootstrap test and SPEC test. Improvements of this patch are shown in llvm/test/CodeGen/PowerPC/constants-i64.ll Reviewed By: steven.zhang, stefanp Differential Revision: https://reviews.llvm.org/D92089
2020-12-21 13:21:07 +08:00
; CHECK-NEXT: rldic 4, 4, 32, 31
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-NEXT: xor 3, 3, 4
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%xor = xor i64 %a, 4294967296
ret i64 %xor
}
define i64 @xori_test_c(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: xori_test_c:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xori 3, 3, 65535
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%xor = xor i64 %a, 65535
ret i64 %xor
}
define i64 @xori_test_d(i64 %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: xori_test_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xoris 3, 3, 1
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%xor = xor i64 %a, 65536
ret i64 %xor
}
define zeroext i32 @xori_test_e(i32 zeroext %a) {
[NFC] [PowerPC] Update and add tests for ori Use script to update test for ori with 32-bit imms, and add test for ori with 64-bit imms.
2020-03-30 17:46:12 +08:00
; CHECK-LABEL: xori_test_e:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xori 3, 3, 65535
; CHECK-NEXT: xoris 3, 3, 255
; CHECK-NEXT: blr
[PowerPC] better instruction selection for OR (XOR) with a 32-bit immediate - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
2017-08-23 16:55:18 +08:00
entry:
%xor = xor i32 %a, 16777215
ret i32 %xor
}