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llvm-project/llvm/test/CodeGen/X86/cmovcmov.ll

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[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=CMOV
; RUN: llc < %s -mtriple=i686-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=NOCMOV
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
; Test 2xCMOV patterns exposed after legalization.
; One way to do that is with (select (fcmp une/oeq)), which gets
; legalized to setp/setne.
define i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) #0 {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: test_select_fcmp_oeq_i32:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: movl %edi, %eax
; CMOV-NEXT: ucomiss %xmm1, %xmm0
; CMOV-NEXT: cmovnel %esi, %eax
; CMOV-NEXT: cmovpl %esi, %eax
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: test_select_fcmp_oeq_i32:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: fucompp
; NOCMOV-NEXT: fnstsw %ax
; NOCMOV-NEXT: # kill: def $ah killed $ah killed $ax
; NOCMOV-NEXT: sahf
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: jne .LBB0_3
; NOCMOV-NEXT: # %bb.1: # %entry
; NOCMOV-NEXT: jp .LBB0_3
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: .LBB0_3: # %entry
; NOCMOV-NEXT: movl (%eax), %eax
; NOCMOV-NEXT: retl
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
entry:
%cmp = fcmp oeq float %a, %b
%r = select i1 %cmp, i32 %c, i32 %d
ret i32 %r
}
define i64 @test_select_fcmp_oeq_i64(float %a, float %b, i64 %c, i64 %d) #0 {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: test_select_fcmp_oeq_i64:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: movq %rdi, %rax
; CMOV-NEXT: ucomiss %xmm1, %xmm0
; CMOV-NEXT: cmovneq %rsi, %rax
; CMOV-NEXT: cmovpq %rsi, %rax
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: test_select_fcmp_oeq_i64:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: fucompp
; NOCMOV-NEXT: fnstsw %ax
; NOCMOV-NEXT: # kill: def $ah killed $ah killed $ax
; NOCMOV-NEXT: sahf
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
; NOCMOV-NEXT: jne .LBB1_3
; NOCMOV-NEXT: # %bb.1: # %entry
; NOCMOV-NEXT: jp .LBB1_3
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
; NOCMOV-NEXT: .LBB1_3: # %entry
; NOCMOV-NEXT: movl (%ecx), %eax
; NOCMOV-NEXT: movl 4(%ecx), %edx
; NOCMOV-NEXT: retl
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
entry:
%cmp = fcmp oeq float %a, %b
%r = select i1 %cmp, i64 %c, i64 %d
ret i64 %r
}
define i64 @test_select_fcmp_une_i64(float %a, float %b, i64 %c, i64 %d) #0 {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: test_select_fcmp_une_i64:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: movq %rsi, %rax
; CMOV-NEXT: ucomiss %xmm1, %xmm0
; CMOV-NEXT: cmovneq %rdi, %rax
; CMOV-NEXT: cmovpq %rdi, %rax
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: test_select_fcmp_une_i64:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: fucompp
; NOCMOV-NEXT: fnstsw %ax
; NOCMOV-NEXT: # kill: def $ah killed $ah killed $ax
; NOCMOV-NEXT: sahf
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
; NOCMOV-NEXT: jne .LBB2_3
; NOCMOV-NEXT: # %bb.1: # %entry
; NOCMOV-NEXT: jp .LBB2_3
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
; NOCMOV-NEXT: .LBB2_3: # %entry
; NOCMOV-NEXT: movl (%ecx), %eax
; NOCMOV-NEXT: movl 4(%ecx), %edx
; NOCMOV-NEXT: retl
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
entry:
%cmp = fcmp une float %a, %b
%r = select i1 %cmp, i64 %c, i64 %d
ret i64 %r
}
define double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) #0 {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: test_select_fcmp_oeq_f64:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: ucomiss %xmm1, %xmm0
; CMOV-NEXT: jne .LBB3_3
; CMOV-NEXT: # %bb.1: # %entry
; CMOV-NEXT: jp .LBB3_3
; CMOV-NEXT: # %bb.2: # %entry
; CMOV-NEXT: movaps %xmm2, %xmm3
; CMOV-NEXT: .LBB3_3: # %entry
; CMOV-NEXT: movaps %xmm3, %xmm0
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: test_select_fcmp_oeq_f64:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: fucompp
; NOCMOV-NEXT: fnstsw %ax
; NOCMOV-NEXT: # kill: def $ah killed $ah killed $ax
; NOCMOV-NEXT: sahf
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: jne .LBB3_3
; NOCMOV-NEXT: # %bb.1: # %entry
; NOCMOV-NEXT: jp .LBB3_3
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: .LBB3_3: # %entry
; NOCMOV-NEXT: fldl (%eax)
; NOCMOV-NEXT: retl
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
entry:
%cmp = fcmp oeq float %a, %b
%r = select i1 %cmp, double %c, double %d
ret double %r
}
define <4 x i32> @test_select_fcmp_oeq_v4i32(float %a, float %b, <4 x i32> %c, <4 x i32> %d) #0 {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: test_select_fcmp_oeq_v4i32:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: ucomiss %xmm1, %xmm0
; CMOV-NEXT: jne .LBB4_3
; CMOV-NEXT: # %bb.1: # %entry
; CMOV-NEXT: jp .LBB4_3
; CMOV-NEXT: # %bb.2: # %entry
; CMOV-NEXT: movaps %xmm2, %xmm3
; CMOV-NEXT: .LBB4_3: # %entry
; CMOV-NEXT: movaps %xmm3, %xmm0
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: test_select_fcmp_oeq_v4i32:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: pushl %edi
; NOCMOV-NEXT: pushl %esi
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: fucompp
; NOCMOV-NEXT: fnstsw %ax
; NOCMOV-NEXT: # kill: def $ah killed $ah killed $ax
; NOCMOV-NEXT: sahf
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: jne .LBB4_3
; NOCMOV-NEXT: # %bb.1: # %entry
; NOCMOV-NEXT: jp .LBB4_3
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: .LBB4_3: # %entry
; NOCMOV-NEXT: movl (%eax), %ecx
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %edx
; NOCMOV-NEXT: jne .LBB4_6
; NOCMOV-NEXT: # %bb.4: # %entry
; NOCMOV-NEXT: jp .LBB4_6
; NOCMOV-NEXT: # %bb.5: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %edx
; NOCMOV-NEXT: .LBB4_6: # %entry
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: movl (%edx), %edx
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %esi
; NOCMOV-NEXT: jne .LBB4_9
; NOCMOV-NEXT: # %bb.7: # %entry
; NOCMOV-NEXT: jp .LBB4_9
; NOCMOV-NEXT: # %bb.8: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %esi
; NOCMOV-NEXT: .LBB4_9: # %entry
; NOCMOV-NEXT: movl (%esi), %esi
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %edi
; NOCMOV-NEXT: jne .LBB4_12
; NOCMOV-NEXT: # %bb.10: # %entry
; NOCMOV-NEXT: jp .LBB4_12
; NOCMOV-NEXT: # %bb.11: # %entry
; NOCMOV-NEXT: leal {{[0-9]+}}(%esp), %edi
; NOCMOV-NEXT: .LBB4_12: # %entry
; NOCMOV-NEXT: movl (%edi), %edi
; NOCMOV-NEXT: movl %edi, 12(%eax)
; NOCMOV-NEXT: movl %esi, 8(%eax)
; NOCMOV-NEXT: movl %edx, 4(%eax)
; NOCMOV-NEXT: movl %ecx, (%eax)
; NOCMOV-NEXT: popl %esi
; NOCMOV-NEXT: popl %edi
; NOCMOV-NEXT: retl $4
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
entry:
%cmp = fcmp oeq float %a, %b
%r = select i1 %cmp, <4 x i32> %c, <4 x i32> %d
ret <4 x i32> %r
}
; Also make sure we catch the original code-sequence of interest:
define float @test_zext_fcmp_une(float %a, float %b) #0 {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: test_zext_fcmp_une:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: ucomiss %xmm1, %xmm0
; CMOV-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CMOV-NEXT: jne .LBB5_3
; CMOV-NEXT: # %bb.1: # %entry
; CMOV-NEXT: jp .LBB5_3
; CMOV-NEXT: # %bb.2: # %entry
; CMOV-NEXT: xorps %xmm0, %xmm0
; CMOV-NEXT: .LBB5_3: # %entry
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: test_zext_fcmp_une:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: fucompp
; NOCMOV-NEXT: fnstsw %ax
; NOCMOV-NEXT: # kill: def $ah killed $ah killed $ax
; NOCMOV-NEXT: sahf
; NOCMOV-NEXT: fld1
; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: jne .LBB5_1
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: jp .LBB5_5
; NOCMOV-NEXT: # %bb.3: # %entry
; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: jmp .LBB5_4
; NOCMOV-NEXT: .LBB5_1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: .LBB5_4: # %entry
; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: .LBB5_5: # %entry
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: retl
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
entry:
%cmp = fcmp une float %a, %b
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
define float @test_zext_fcmp_oeq(float %a, float %b) #0 {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: test_zext_fcmp_oeq:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: ucomiss %xmm1, %xmm0
; CMOV-NEXT: xorps %xmm0, %xmm0
; CMOV-NEXT: jne .LBB6_3
; CMOV-NEXT: # %bb.1: # %entry
; CMOV-NEXT: jp .LBB6_3
; CMOV-NEXT: # %bb.2: # %entry
; CMOV-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CMOV-NEXT: .LBB6_3: # %entry
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: test_zext_fcmp_oeq:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: fucompp
; NOCMOV-NEXT: fnstsw %ax
; NOCMOV-NEXT: # kill: def $ah killed $ah killed $ax
; NOCMOV-NEXT: sahf
; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fld1
; NOCMOV-NEXT: jne .LBB6_1
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: jp .LBB6_5
; NOCMOV-NEXT: # %bb.3: # %entry
; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: jmp .LBB6_4
; NOCMOV-NEXT: .LBB6_1:
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: .LBB6_4: # %entry
; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: .LBB6_5: # %entry
; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: retl
[X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)). Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
2015-03-03 09:09:14 +08:00
entry:
%cmp = fcmp oeq float %a, %b
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
attributes #0 = { nounwind }
X86ISelLowering: Fix cmov(cmov) special lowering bug There's a special case in EmitLoweredSelect() that produces an improved lowering for cmov(cmov) patterns. However this special lowering is currently broken if the inner cmov has multiple users so this patch stops using it in this case. If you wonder why this wasn't fixed by continuing to use the special lowering and inserting a 2nd PHI for the inner cmov: I believe this would incur additional copies/register pressure so the special lowering does not improve upon the normal one anymore in this case. This fixes http://llvm.org/PR26256 (= rdar://24329747) llvm-svn: 258729
2016-01-26 06:08:25 +08:00
@g8 = global i8 0
; The following test failed because llvm had a bug where a structure like:
;
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
2017-12-07 18:40:31 +08:00
; %12 = CMOV_GR8 %7, %11 ... (lt)
; %13 = CMOV_GR8 %12, %11 ... (gt)
X86ISelLowering: Fix cmov(cmov) special lowering bug There's a special case in EmitLoweredSelect() that produces an improved lowering for cmov(cmov) patterns. However this special lowering is currently broken if the inner cmov has multiple users so this patch stops using it in this case. If you wonder why this wasn't fixed by continuing to use the special lowering and inserting a 2nd PHI for the inner cmov: I believe this would incur additional copies/register pressure so the special lowering does not improve upon the normal one anymore in this case. This fixes http://llvm.org/PR26256 (= rdar://24329747) llvm-svn: 258729
2016-01-26 06:08:25 +08:00
;
; was lowered to:
;
; The first two cmovs got expanded to:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; %bb.0:
; JL_1 %bb.9
; %bb.7:
; JG_1 %bb.9
; %bb.8:
; %bb.9:
; %12 = phi(%7, %bb.8, %11, %bb.0, %12, %bb.7)
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
2017-11-30 20:12:19 +08:00
; %13 = COPY %12
; Which was invalid as %12 is not the same value as %13
X86ISelLowering: Fix cmov(cmov) special lowering bug There's a special case in EmitLoweredSelect() that produces an improved lowering for cmov(cmov) patterns. However this special lowering is currently broken if the inner cmov has multiple users so this patch stops using it in this case. If you wonder why this wasn't fixed by continuing to use the special lowering and inserting a 2nd PHI for the inner cmov: I believe this would incur additional copies/register pressure so the special lowering does not improve upon the normal one anymore in this case. This fixes http://llvm.org/PR26256 (= rdar://24329747) llvm-svn: 258729
2016-01-26 06:08:25 +08:00
define void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) {
[X86][NFC] Autogenerate check lines in cmovcmov.ll test Investigating 8-bit cmov promotion, this test comes up. llvm-svn: 355496
2019-03-06 19:47:43 +08:00
; CMOV-LABEL: no_cascade_opt:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: cmpl %edx, %esi
; CMOV-NEXT: movb $20, %al
; CMOV-NEXT: movb $20, %dl
; CMOV-NEXT: jge .LBB7_1
; CMOV-NEXT: # %bb.2: # %entry
; CMOV-NEXT: jle .LBB7_3
; CMOV-NEXT: .LBB7_4: # %entry
; CMOV-NEXT: testl %edi, %edi
; CMOV-NEXT: jne .LBB7_5
; CMOV-NEXT: .LBB7_6: # %entry
; CMOV-NEXT: movb %al, {{.*}}(%rip)
; CMOV-NEXT: retq
; CMOV-NEXT: .LBB7_1: # %entry
; CMOV-NEXT: movl %ecx, %edx
; CMOV-NEXT: jg .LBB7_4
; CMOV-NEXT: .LBB7_3: # %entry
; CMOV-NEXT: movl %edx, %eax
; CMOV-NEXT: testl %edi, %edi
; CMOV-NEXT: je .LBB7_6
; CMOV-NEXT: .LBB7_5: # %entry
; CMOV-NEXT: movl %edx, %eax
; CMOV-NEXT: movb %al, {{.*}}(%rip)
; CMOV-NEXT: retq
;
; NOCMOV-LABEL: no_cascade_opt:
; NOCMOV: # %bb.0: # %entry
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: movb $20, %al
; NOCMOV-NEXT: movb $20, %cl
; NOCMOV-NEXT: jge .LBB7_1
; NOCMOV-NEXT: # %bb.2: # %entry
; NOCMOV-NEXT: jle .LBB7_3
; NOCMOV-NEXT: .LBB7_4: # %entry
; NOCMOV-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; NOCMOV-NEXT: jne .LBB7_5
; NOCMOV-NEXT: .LBB7_6: # %entry
; NOCMOV-NEXT: movb %al, g8
; NOCMOV-NEXT: retl
; NOCMOV-NEXT: .LBB7_1: # %entry
; NOCMOV-NEXT: movb {{[0-9]+}}(%esp), %cl
; NOCMOV-NEXT: jg .LBB7_4
; NOCMOV-NEXT: .LBB7_3: # %entry
; NOCMOV-NEXT: movl %ecx, %eax
; NOCMOV-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; NOCMOV-NEXT: je .LBB7_6
; NOCMOV-NEXT: .LBB7_5: # %entry
; NOCMOV-NEXT: movl %ecx, %eax
; NOCMOV-NEXT: movb %al, g8
; NOCMOV-NEXT: retl
X86ISelLowering: Fix cmov(cmov) special lowering bug There's a special case in EmitLoweredSelect() that produces an improved lowering for cmov(cmov) patterns. However this special lowering is currently broken if the inner cmov has multiple users so this patch stops using it in this case. If you wonder why this wasn't fixed by continuing to use the special lowering and inserting a 2nd PHI for the inner cmov: I believe this would incur additional copies/register pressure so the special lowering does not improve upon the normal one anymore in this case. This fixes http://llvm.org/PR26256 (= rdar://24329747) llvm-svn: 258729
2016-01-26 06:08:25 +08:00
entry:
%c0 = icmp eq i32 %v0, 0
%c1 = icmp slt i32 %v1, %v2
%c2 = icmp sgt i32 %v1, %v2
%trunc = trunc i32 %v3 to i8
%sel0 = select i1 %c1, i8 20, i8 %trunc
%sel1 = select i1 %c2, i8 20, i8 %sel0
%sel2 = select i1 %c0, i8 %sel1, i8 %sel0
store volatile i8 %sel2, i8* @g8
ret void
}