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Revert "RegScavenging: Add scavengeRegisterBackwards()" Revert because of reports of some PPC input starting to spill when it was predicted that it wouldn't and no spillslot was reserved. This reverts commit r305516. llvm-svn: 305566
2017-06-17 01:48:08 +08:00
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
; Check that register scavenging spill slot is close to $fp.
target triple="mipsel--"
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64 problems reported in the stage2 build last time, which I cannot reproduce right now. This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305516
2017-06-16 06:14:55 +08:00
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
@var = external global i32
@ptrvar = external global i8*
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64 problems reported in the stage2 build last time, which I cannot reproduce right now. This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305516
2017-06-16 06:14:55 +08:00
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
; CHECK-LABEL: func:
define void @func() {
%space = alloca i32, align 4
%stackspace = alloca[16384 x i32], align 4
; ensure stackspace is not optimized out
%stackspace_casted = bitcast [16384 x i32]* %stackspace to i8*
store volatile i8* %stackspace_casted, i8** @ptrvar
Revert "RegScavenging: Add scavengeRegisterBackwards()" Revert because of reports of some PPC input starting to spill when it was predicted that it wouldn't and no spillslot was reserved. This reverts commit r305516. llvm-svn: 305566
2017-06-17 01:48:08 +08:00
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
; Load values to increase register pressure.
%v0 = load volatile i32, i32* @var
%v1 = load volatile i32, i32* @var
%v2 = load volatile i32, i32* @var
%v3 = load volatile i32, i32* @var
%v4 = load volatile i32, i32* @var
%v5 = load volatile i32, i32* @var
%v6 = load volatile i32, i32* @var
%v7 = load volatile i32, i32* @var
%v8 = load volatile i32, i32* @var
%v9 = load volatile i32, i32* @var
%v10 = load volatile i32, i32* @var
%v11 = load volatile i32, i32* @var
%v12 = load volatile i32, i32* @var
%v13 = load volatile i32, i32* @var
%v14 = load volatile i32, i32* @var
%v15 = load volatile i32, i32* @var
%v16 = load volatile i32, i32* @var
; Computing a stack-relative values needs an additional register.
; We should get an emergency spill/reload for this.
; CHECK: sw ${{.*}}, 0($sp)
; CHECK: lw ${{.*}}, 0($sp)
store volatile i32 %v0, i32* %space
; store values so they are used.
store volatile i32 %v0, i32* @var
store volatile i32 %v1, i32* @var
store volatile i32 %v2, i32* @var
store volatile i32 %v3, i32* @var
store volatile i32 %v4, i32* @var
store volatile i32 %v5, i32* @var
store volatile i32 %v6, i32* @var
store volatile i32 %v7, i32* @var
store volatile i32 %v8, i32* @var
store volatile i32 %v9, i32* @var
store volatile i32 %v10, i32* @var
store volatile i32 %v11, i32* @var
store volatile i32 %v12, i32* @var
store volatile i32 %v13, i32* @var
store volatile i32 %v14, i32* @var
store volatile i32 %v15, i32* @var
store volatile i32 %v16, i32* @var
ret void
}