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llvm-project/llvm/test/CodeGen/X86/vector-shuffle-masked.ll

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[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+avx512bw | FileCheck %s --check-prefix=CHECK
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
define <4 x i32> @mask_shuffle_v4i32_1234(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v4i32_1234:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignd {{.*#+}} xmm2 {%k1} = xmm0[1,2,3],xmm1[0]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %xmm2, %xmm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x i32> @maskz_shuffle_v4i32_1234(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v4i32_1234:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignd {{.*#+}} xmm0 {%k1} {z} = xmm0[1,2,3],xmm1[0]
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
define <4 x i32> @mask_shuffle_v4i32_2345(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v4i32_2345:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignd {{.*#+}} xmm2 {%k1} = xmm0[2,3],xmm1[0,1]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %xmm2, %xmm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x i32> @maskz_shuffle_v4i32_2345(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v4i32_2345:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignd {{.*#+}} xmm0 {%k1} {z} = xmm0[2,3],xmm1[0,1]
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
define <2 x i64> @mask_shuffle_v2i64_12(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v2i64_12:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignq {{.*#+}} xmm2 {%k1} = xmm0[1],xmm1[0]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %xmm2, %xmm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> %passthru
ret <2 x i64> %res
}
define <2 x i64> @maskz_shuffle_v2i64_12(<2 x i64> %a, <2 x i64> %b, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v2i64_12:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignq {{.*#+}} xmm0 {%k1} {z} = xmm0[1],xmm1[0]
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> zeroinitializer
ret <2 x i64> %res
}
define <4 x i64> @mask_shuffle_v4i64_1234(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v4i64_1234:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: valignq {{.*#+}} ymm2 {%k1} = ymm0[1,2,3],ymm1[0]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %ymm2, %ymm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> %passthru
ret <4 x i64> %res
}
define <4 x i64> @maskz_shuffle_v4i64_1234(<4 x i64> %a, <4 x i64> %b, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v4i64_1234:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: valignq {{.*#+}} ymm0 {%k1} {z} = ymm0[1,2,3],ymm1[0]
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> zeroinitializer
ret <4 x i64> %res
}
define <4 x i64> @mask_shuffle_v4i64_1230(<4 x i64> %a, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v4i64_1230:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: vpermq {{.*#+}} ymm1 {%k1} = ymm0[1,2,3,0]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %ymm1, %ymm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> %passthru
ret <4 x i64> %res
}
define <4 x i64> @maskz_shuffle_v4i64_1230(<4 x i64> %a, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v4i64_1230:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: vpermq {{.*#+}} ymm0 {%k1} {z} = ymm0[1,2,3,0]
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> zeroinitializer
ret <4 x i64> %res
}
define <8 x i32> @mask_shuffle_v8i32_12345678(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v8i32_12345678:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: valignd {{.*#+}} ymm2 {%k1} = ymm0[1,2,3,4,5,6,7],ymm1[0]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %ymm2, %ymm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> %passthru
ret <8 x i32> %res
}
define <8 x i32> @maskz_shuffle_v8i32_12345678(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v8i32_12345678:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: valignd {{.*#+}} ymm0 {%k1} {z} = ymm0[1,2,3,4,5,6,7],ymm1[0]
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
define <8 x i32> @mask_shuffle_v8i32_23456789(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v8i32_23456789:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignd {{.*#+}} ymm2 {%k1} = ymm0[2,3,4,5,6,7],ymm1[0,1]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %ymm2, %ymm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> %passthru
ret <8 x i32> %res
}
define <8 x i32> @maskz_shuffle_v8i32_23456789(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v8i32_23456789:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type Summary: Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking. This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018. I plan to add support for more operations in future patches. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26902 llvm-svn: 287612
2016-11-22 11:51:53 +08:00
; CHECK-NEXT: valignd {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3,4,5,6,7],ymm1[0,1]
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
define <8 x i32> @mask_shuffle_v8i32_12345670(<8 x i32> %a, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v8i32_12345670:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: valignd {{.*#+}} ymm1 {%k1} = ymm0[1,2,3,4,5,6,7,0]
This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers. The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled. Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky Differential Revision: https://reviews.llvm.org/D27901 llvm-svn: 290663
2016-12-28 18:12:48 +08:00
; CHECK-NEXT: vmovdqa %ymm1, %ymm0
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> %passthru
ret <8 x i32> %res
}
define <8 x i32> @maskz_shuffle_v8i32_12345670(<8 x i32> %a, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v8i32_12345670:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: valignd {{.*#+}} ymm0 {%k1} {z} = ymm0[1,2,3,4,5,6,7,0]
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
define <8 x i32> @mask_shuffle_v8i32_23456701(<8 x i32> %a, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_shuffle_v8i32_23456701:
; CHECK: # BB#0:
; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,2,3,0]
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Teach two address instruction pass to replace masked move instructions with blendm instructions when its beneficial. Isel now selects masked move instructions for vselect instead of blendm. But sometimes it beneficial to register allocation to remove the tied register constraint by using blendm instructions. This also picks up cases where the masked move was created due to a masked load intrinsic. Differential Revision: https://reviews.llvm.org/D28454 llvm-svn: 292005
2017-01-14 15:50:52 +08:00
; CHECK-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> %passthru
ret <8 x i32> %res
}
define <8 x i32> @maskz_shuffle_v8i32_23456701(<8 x i32> %a, i8 %mask) {
; CHECK-LABEL: maskz_shuffle_v8i32_23456701:
; CHECK: # BB#0:
; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,2,3,0]
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add tests for masked palignr/valignd/valignq shuffles, many of which show failures to fold the masking into the operation. Many of these problems are because shuffle lowering widens element size and reduces element count when possible. This causes the shuffle to become separated from the select by a bitcast. Future patches will work to improve these cases by rewriting the shuffle back to a narrow element type if we think it can result in folding the mask. llvm-svn: 287503
2016-11-21 03:50:32 +08:00
; CHECK-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x i32> @mask_extract_v8i32_v4i32_0(<8 x i32> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i32_v4i32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x i32> @mask_extract_v8i32_v4i32_0_z(<8 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i32_v4i32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
define <4 x i32> @mask_extract_v8i32_v4i32_1(<8 x i32> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i32_v4i32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti32x4 $1, %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x i32> @mask_extract_v8i32_v4i32_1_z(<8 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i32_v4i32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti32x4 $1, %ymm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
define <4 x float> @mask_extract_v8f32_v4f32_0(<8 x float> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f32_v4f32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> %passthru
ret <4 x float> %res
}
define <4 x float> @mask_extract_v8f32_v4f32_0_z(<8 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f32_v4f32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovaps %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> zeroinitializer
ret <4 x float> %res
}
define <4 x float> @mask_extract_v8f32_v4f32_1(<8 x float> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f32_v4f32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf32x4 $1, %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> %passthru
ret <4 x float> %res
}
define <4 x float> @mask_extract_v8f32_v4f32_1_z(<8 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f32_v4f32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf32x4 $1, %ymm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> zeroinitializer
ret <4 x float> %res
}
define <2 x i64> @mask_extract_v4i64_v2i64_0(<4 x i64> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v4i64_v2i64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> %passthru
ret <2 x i64> %res
}
define <2 x i64> @mask_extract_v4i64_v2i64_0_z(<4 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v4i64_v2i64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> zeroinitializer
ret <2 x i64> %res
}
define <2 x i64> @mask_extract_v4i64_v2i64_1(<4 x i64> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v4i64_v2i64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti64x2 $1, %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> %passthru
ret <2 x i64> %res
}
define <2 x i64> @mask_extract_v4i64_v2i64_1_z(<4 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v4i64_v2i64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti64x2 $1, %ymm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x i64> %a, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> zeroinitializer
ret <2 x i64> %res
}
define <2 x double> @mask_extract_v4f64_v2f64_0(<4 x double> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v4f64_v2f64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vblendmpd %xmm0, %xmm1, %xmm0 {%k1}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> %passthru
ret <2 x double> %res
}
define <2 x double> @mask_extract_v4f64_v2f64_0_z(<4 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v4f64_v2f64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovapd %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> zeroinitializer
ret <2 x double> %res
}
define <2 x double> @mask_extract_v4f64_v2f64_1(<4 x double> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v4f64_v2f64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf64x2 $1, %ymm0, %xmm1 {%k1}
; CHECK-NEXT: vmovapd %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> %passthru
ret <2 x double> %res
}
define <2 x double> @mask_extract_v4f64_v2f64_1_z(<4 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v4f64_v2f64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf64x2 $1, %ymm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> zeroinitializer
ret <2 x double> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x i32> @mask_extract_v16i32_v4i32_0(<16 x i32> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v4i32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x i32> @mask_extract_v16i32_v4i32_0_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v4i32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x i32> @mask_extract_v16i32_v4i32_1(<16 x i32> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v4i32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti32x4 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x i32> @mask_extract_v16i32_v4i32_1_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v4i32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti32x4 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x i32> @mask_extract_v16i32_v4i32_2(<16 x i32> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v4i32_2:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti32x4 $2, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x i32> @mask_extract_v16i32_v4i32_3(<16 x i32> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v4i32_3:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x float> @mask_extract_v16f32_v4f32_0(<16 x float> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v4f32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> %passthru
ret <4 x float> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x float> @mask_extract_v16f32_v4f32_0_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v4f32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovaps %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> zeroinitializer
ret <4 x float> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x float> @mask_extract_v16f32_v4f32_1(<16 x float> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v4f32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf32x4 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> %passthru
ret <4 x float> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x float> @mask_extract_v16f32_v4f32_1_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v4f32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf32x4 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> zeroinitializer
ret <4 x float> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x float> @mask_extract_v16f32_v4f32_2(<16 x float> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v4f32_2:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf32x4 $2, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> %passthru
ret <4 x float> %res
}
define <4 x float> @mask_extract_v16f32_v4f32_3(<16 x float> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v4f32_3:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf32x4 $3, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle, <4 x float> %passthru
ret <4 x float> %res
}
define <8 x i32> @mask_extract_v16i32_v8i32_0(<16 x i32> %a, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v8i32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> %passthru
ret <8 x i32> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <8 x i32> @mask_extract_v16i32_v8i32_0_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v8i32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <8 x i32> @mask_extract_v16i32_v8i32_1(<16 x i32> %a, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v8i32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti32x8 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovdqa %ymm1, %ymm0
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> %passthru
ret <8 x i32> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <8 x i32> @mask_extract_v16i32_v8i32_1_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16i32_v8i32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti32x8 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <8 x float> @mask_extract_v16f32_v8f32_0(<16 x float> %a, <8 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v8f32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vblendmps %ymm0, %ymm1, %ymm0 {%k1}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle, <8 x float> %passthru
ret <8 x float> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <8 x float> @mask_extract_v16f32_v8f32_0_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v8f32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovaps %ymm0, %ymm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle, <8 x float> zeroinitializer
ret <8 x float> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <8 x float> @mask_extract_v16f32_v8f32_1(<16 x float> %a, <8 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v8f32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf32x8 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovaps %ymm1, %ymm0
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle, <8 x float> %passthru
ret <8 x float> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <8 x float> @mask_extract_v16f32_v8f32_1_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v16f32_v8f32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf32x8 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle, <8 x float> zeroinitializer
ret <8 x float> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <2 x i64> @mask_extract_v8i64_v2i64_0(<8 x i64> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v2i64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> %passthru
ret <2 x i64> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <2 x i64> @mask_extract_v8i64_v2i64_0_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v2i64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> zeroinitializer
ret <2 x i64> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <2 x i64> @mask_extract_v8i64_v2i64_1(<8 x i64> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v2i64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti64x2 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> %passthru
ret <2 x i64> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <2 x i64> @mask_extract_v8i64_v2i64_1_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v2i64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti64x2 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> zeroinitializer
ret <2 x i64> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <2 x i64> @mask_extract_v8i64_v2i64_2(<8 x i64> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v2i64_2:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti64x2 $2, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 4, i32 5>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> %passthru
ret <2 x i64> %res
}
define <2 x i64> @mask_extract_v8i64_v2i64_3(<8 x i64> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v2i64_3:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti64x2 $3, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle, <2 x i64> %passthru
ret <2 x i64> %res
}
define <2 x double> @mask_extract_v8f64_v2f64_0(<8 x double> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v2f64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vblendmpd %xmm0, %xmm1, %xmm0 {%k1}
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> %passthru
ret <2 x double> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <2 x double> @mask_extract_v8f64_v2f64_0_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v2f64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovapd %xmm0, %xmm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> zeroinitializer
ret <2 x double> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <2 x double> @mask_extract_v8f64_v2f64_1(<8 x double> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v2f64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf64x2 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovapd %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> %passthru
ret <2 x double> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <2 x double> @mask_extract_v8f64_v2f64_1_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v2f64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf64x2 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> zeroinitializer
ret <2 x double> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <2 x double> @mask_extract_v8f64_v2f64_2(<8 x double> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v2f64_2:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf64x2 $2, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovapd %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> %passthru
ret <2 x double> %res
}
define <2 x double> @mask_extract_v8f64_v2f64_3(<8 x double> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v2f64_3:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf64x2 $3, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovapd %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle, <2 x double> %passthru
ret <2 x double> %res
}
define <4 x i64> @mask_extract_v8i64_v4i64_0(<8 x i64> %a, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v4i64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> %passthru
ret <4 x i64> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x i64> @mask_extract_v8i64_v4i64_0_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v4i64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> zeroinitializer
ret <4 x i64> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x i64> @mask_extract_v8i64_v4i64_1(<8 x i64> %a, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v4i64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovdqa %ymm1, %ymm0
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> %passthru
ret <4 x i64> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x i64> @mask_extract_v8i64_v4i64_1_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8i64_v4i64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle, <4 x i64> zeroinitializer
ret <4 x i64> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x double> @mask_extract_v8f64_v4f64_0(<8 x double> %a, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v4f64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vblendmpd %ymm0, %ymm1, %ymm0 {%k1}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle, <4 x double> %passthru
ret <4 x double> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x double> @mask_extract_v8f64_v4f64_0_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v4f64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
2017-08-26 07:34:59 +08:00
; CHECK-NEXT: vmovapd %ymm0, %ymm0 {%k1} {z}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle, <4 x double> zeroinitializer
ret <4 x double> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x double> @mask_extract_v8f64_v4f64_1(<8 x double> %a, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v4f64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovapd %ymm1, %ymm0
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle, <4 x double> %passthru
ret <4 x double> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <4 x double> @mask_extract_v8f64_v4f64_1_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_extract_v8f64_v4f64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle, <4 x double> zeroinitializer
ret <4 x double> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <8 x i32> @mask_cast_extract_v8i64_v8i32_0(<8 x i64> %a, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v8i32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x i64> %shuffle to <8 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle.cast, <8 x i32> %passthru
ret <8 x i32> %res
}
define <8 x i32> @mask_cast_extract_v8i64_v8i32_0_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v8i32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x i64> %shuffle to <8 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle.cast, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <8 x i32> @mask_cast_extract_v8i64_v8i32_1(<8 x i64> %a, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v8i32_1:
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextracti32x8 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovdqa %ymm1, %ymm0
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x i64> %shuffle to <8 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle.cast, <8 x i32> %passthru
ret <8 x i32> %res
}
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <8 x i32> @mask_cast_extract_v8i64_v8i32_1_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v8i32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextracti32x8 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x i64> %shuffle to <8 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuffle.cast, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <8 x float> @mask_cast_extract_v8f64_v8f32_0(<8 x double> %a, <8 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v8f32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vblendmps %ymm0, %ymm1, %ymm0 {%k1}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x double> %shuffle to <8 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle.cast, <8 x float> %passthru
ret <8 x float> %res
}
define <8 x float> @mask_cast_extract_v8f64_v8f32_0_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v8f32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovaps %ymm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x double> %shuffle to <8 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle.cast, <8 x float> zeroinitializer
ret <8 x float> %res
}
[AVX512] Add additional test cases for masked extract subvector. This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
2017-08-26 07:34:57 +08:00
define <8 x float> @mask_cast_extract_v8f64_v8f32_1(<8 x double> %a, <8 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v8f32_1:
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextractf32x8 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovaps %ymm1, %ymm0
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x double> %shuffle to <8 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle.cast, <8 x float> %passthru
ret <8 x float> %res
}
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <8 x float> @mask_cast_extract_v8f64_v8f32_1_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v8f32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextractf32x8 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x double> %shuffle to <8 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuffle.cast, <8 x float> zeroinitializer
ret <8 x float> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <4 x i32> @mask_cast_extract_v8i64_v4i32_0(<8 x i64> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v4i32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
%shuffle.cast = bitcast <2 x i64> %shuffle to <4 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle.cast, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x i32> @mask_cast_extract_v8i64_v4i32_0_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v4i32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
%shuffle.cast = bitcast <2 x i64> %shuffle to <4 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle.cast, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x i32> @mask_cast_extract_v8i64_v4i32_1(<8 x i64> %a, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v4i32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextracti32x4 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 2, i32 3>
%shuffle.cast = bitcast <2 x i64> %shuffle to <4 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle.cast, <4 x i32> %passthru
ret <4 x i32> %res
}
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <4 x i32> @mask_cast_extract_v8i64_v4i32_1_z(<8 x i64> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8i64_v4i32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextracti32x4 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x i64> %a, <8 x i64> undef, <2 x i32> <i32 2, i32 3>
%shuffle.cast = bitcast <2 x i64> %shuffle to <4 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuffle.cast, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <4 x float> @mask_cast_extract_v8f64_v4f32_0(<8 x double> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v4f32_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%shuffle.cast = bitcast <2 x double> %shuffle to <4 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle.cast, <4 x float> %passthru
ret <4 x float> %res
}
define <4 x float> @mask_cast_extract_v8f64_v4f32_0_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v4f32_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovaps %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%shuffle.cast = bitcast <2 x double> %shuffle to <4 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle.cast, <4 x float> zeroinitializer
ret <4 x float> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x float> @mask_cast_extract_v8f64_v4f32_1(<8 x double> %a, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v4f32_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextractf32x4 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovaps %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%shuffle.cast = bitcast <2 x double> %shuffle to <4 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle.cast, <4 x float> %passthru
ret <4 x float> %res
}
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <4 x float> @mask_cast_extract_v8f64_v4f32_1_z(<8 x double> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v8f64_v4f32_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextractf32x4 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <8 x double> %a, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%shuffle.cast = bitcast <2 x double> %shuffle to <4 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuffle.cast, <4 x float> zeroinitializer
ret <4 x float> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <4 x i64> @mask_cast_extract_v16i32_v4i64_0(<16 x i32> %a, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v4i64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <8 x i32> %shuffle to <4 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle.cast, <4 x i64> %passthru
ret <4 x i64> %res
}
define <4 x i64> @mask_cast_extract_v16i32_v4i64_0_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v4i64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovdqa64 %ymm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <8 x i32> %shuffle to <4 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle.cast, <4 x i64> zeroinitializer
ret <4 x i64> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x i64> @mask_cast_extract_v16i32_v4i64_1(<16 x i32> %a, <4 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v4i64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovdqa %ymm1, %ymm0
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%shuffle.cast = bitcast <8 x i32> %shuffle to <4 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle.cast, <4 x i64> %passthru
ret <4 x i64> %res
}
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <4 x i64> @mask_cast_extract_v16i32_v4i64_1_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v4i64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%shuffle.cast = bitcast <8 x i32> %shuffle to <4 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %shuffle.cast, <4 x i64> zeroinitializer
ret <4 x i64> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <4 x double> @mask_cast_extract_v16f32_v4f64_0(<16 x float> %a, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v4f64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vblendmpd %ymm0, %ymm1, %ymm0 {%k1}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <8 x float> %shuffle to <4 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle.cast, <4 x double> %passthru
ret <4 x double> %res
}
define <4 x double> @mask_cast_extract_v16f32_v4f64_0_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v4f64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovapd %ymm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <8 x float> %shuffle to <4 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle.cast, <4 x double> zeroinitializer
ret <4 x double> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <4 x double> @mask_cast_extract_v16f32_v4f64_1(<16 x float> %a, <4 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v4f64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm1 {%k1}
; CHECK-NEXT: vmovapd %ymm1, %ymm0
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%shuffle.cast = bitcast <8 x float> %shuffle to <4 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle.cast, <4 x double> %passthru
ret <4 x double> %res
}
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <4 x double> @mask_cast_extract_v16f32_v4f64_1_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v4f64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm0 {%k1} {z}
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%shuffle.cast = bitcast <8 x float> %shuffle to <4 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %shuffle.cast, <4 x double> zeroinitializer
ret <4 x double> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <2 x i64> @mask_cast_extract_v16i32_v2i64_0(<16 x i32> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v2i64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x i32> %shuffle to <2 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle.cast, <2 x i64> %passthru
ret <2 x i64> %res
}
define <2 x i64> @mask_cast_extract_v16i32_v2i64_0_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v2i64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x i32> %shuffle to <2 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle.cast, <2 x i64> zeroinitializer
ret <2 x i64> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <2 x i64> @mask_cast_extract_v16i32_v2i64_1(<16 x i32> %a, <2 x i64> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v2i64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextracti64x2 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x i32> %shuffle to <2 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle.cast, <2 x i64> %passthru
ret <2 x i64> %res
}
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <2 x i64> @mask_cast_extract_v16i32_v2i64_1_z(<16 x i32> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16i32_v2i64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextracti64x2 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x i32> %a, <16 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x i32> %shuffle to <2 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x i64> %shuffle.cast, <2 x i64> zeroinitializer
ret <2 x i64> %res
}
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
define <2 x double> @mask_cast_extract_v16f32_v2f64_0(<16 x float> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v2f64_0:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vblendmpd %xmm0, %xmm1, %xmm0 {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x float> %shuffle to <2 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle.cast, <2 x double> %passthru
ret <2 x double> %res
}
define <2 x double> @mask_cast_extract_v16f32_v2f64_0_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v2f64_0_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
2017-08-28 03:03:36 +08:00
; CHECK-NEXT: vmovapd %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.cast = bitcast <4 x float> %shuffle to <2 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle.cast, <2 x double> zeroinitializer
ret <2 x double> %res
}
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
define <2 x double> @mask_cast_extract_v16f32_v2f64_1(<16 x float> %a, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v2f64_1:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp. llvm-svn: 291214
2017-01-06 13:18:48 +08:00
; CHECK-NEXT: vextractf64x2 $1, %zmm0, %xmm1 {%k1}
; CHECK-NEXT: vmovapd %xmm1, %xmm0
[X86] Generate VZEROUPPER for Skylake-avx512. VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be. Differential Revision: https://reviews.llvm.org/D29874 llvm-svn: 296859
2017-03-03 17:03:24 +08:00
; CHECK-NEXT: vzeroupper
[AVX-512] Add more masked vector extract test cases with and without a bitcast between the select. The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit. llvm-svn: 291213
2017-01-06 13:18:44 +08:00
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x float> %shuffle to <2 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle.cast, <2 x double> %passthru
ret <2 x double> %res
}
[AVX-512] Add masked forms of the alternate MOVDDUP patterns. I'm not too sure how to get isel to select even all of the unmasked forms, but at least we have a consistent set now. llvm-svn: 291368
2017-01-08 06:20:23 +08:00
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
define <2 x double> @mask_cast_extract_v16f32_v2f64_1_z(<16 x float> %a, i8 %mask) {
; CHECK-LABEL: mask_cast_extract_v16f32_v2f64_1_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
2017-08-27 06:24:57 +08:00
; CHECK-NEXT: vextractf64x2 $1, %zmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%shuffle = shufflevector <16 x float> %a, <16 x float> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%shuffle.cast = bitcast <4 x float> %shuffle to <2 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %shuffle.cast, <2 x double> zeroinitializer
ret <2 x double> %res
}
[AVX-512] Add masked forms of the alternate MOVDDUP patterns. I'm not too sure how to get isel to select even all of the unmasked forms, but at least we have a consistent set now. llvm-svn: 291368
2017-01-08 06:20:23 +08:00
define <2 x double> @broadcast_v4f32_0101_from_v2f32_mask(double* %x, <2 x double> %passthru, i8 %mask) {
; CHECK-LABEL: broadcast_v4f32_0101_from_v2f32_mask:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Remove patterns from the other VBLENDM instructions. They are all redundant with masked move instructions. We should probably teach the two address instruction pass to turn masked moves into BLENDM when its beneficial to the register allocator. llvm-svn: 291371
2017-01-08 06:20:34 +08:00
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 {%k1} = mem[0,0]
[AVX-512] Add masked forms of the alternate MOVDDUP patterns. I'm not too sure how to get isel to select even all of the unmasked forms, but at least we have a consistent set now. llvm-svn: 291368
2017-01-08 06:20:23 +08:00
; CHECK-NEXT: retq
%q = load double, double* %x, align 1
%vecinit.i = insertelement <2 x double> undef, double %q, i32 0
%vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %vecinit2.i, <2 x double> %passthru
ret <2 x double> %res
}
define <2 x double> @broadcast_v4f32_0101_from_v2f32_maskz(double* %x, i8 %mask) {
; CHECK-LABEL: broadcast_v4f32_0101_from_v2f32_maskz:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add masked forms of the alternate MOVDDUP patterns. I'm not too sure how to get isel to select even all of the unmasked forms, but at least we have a consistent set now. llvm-svn: 291368
2017-01-08 06:20:23 +08:00
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 {%k1} {z} = mem[0,0]
; CHECK-NEXT: retq
%q = load double, double* %x, align 1
%vecinit.i = insertelement <2 x double> undef, double %q, i32 0
%vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%res = select <2 x i1> %mask.extract, <2 x double> %vecinit2.i, <2 x double> zeroinitializer
ret <2 x double> %res
}
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
define <8 x float> @test_broadcast_2f64_8f32(<2 x double> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_2f64_8f32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 {%k1} {z} = mem[0,1,2,3,0,1,2,3]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <2 x double>, <2 x double> *%p
%2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%3 = bitcast <4 x double> %2 to <8 x float>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %3, <8 x float> zeroinitializer
ret <8 x float> %res
}
define <8 x i32> @test_broadcast_2i64_8i32(<2 x i64> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_2i64_8i32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 {%k1} {z} = mem[0,1,2,3,0,1,2,3]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <2 x i64>, <2 x i64> *%p
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%3 = bitcast <4 x i64> %2 to <8 x i32>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %3, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
define <16 x float> @test_broadcast_2f64_16f32(<2 x double> *%p, i16 %mask) nounwind {
; CHECK-LABEL: test_broadcast_2f64_16f32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcastf32x4 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <2 x double>, <2 x double> *%p
%2 = shufflevector <2 x double> %1, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%3 = bitcast <8 x double> %2 to <16 x float>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x float> %3, <16 x float> zeroinitializer
ret <16 x float> %res
}
define <16 x i32> @test_broadcast_2i64_16i32(<2 x i64> *%p, i16 %mask) nounwind {
; CHECK-LABEL: test_broadcast_2i64_16i32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcasti32x4 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <2 x i64>, <2 x i64> *%p
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%3 = bitcast <8 x i64> %2 to <16 x i32>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x i32> %3, <16 x i32> zeroinitializer
ret <16 x i32> %res
}
define <16 x float> @test_broadcast_4f64_16f32(<4 x double> *%p, i16 %mask) nounwind {
; CHECK-LABEL: test_broadcast_4f64_16f32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcastf32x8 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <4 x double>, <4 x double> *%p
%2 = shufflevector <4 x double> %1, <4 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = bitcast <8 x double> %2 to <16 x float>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x float> %3, <16 x float> zeroinitializer
ret <16 x float> %res
}
define <16 x i32> @test_broadcast_4i64_16i32(<4 x i64> *%p, i16 %mask) nounwind {
; CHECK-LABEL: test_broadcast_4i64_16i32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcasti32x8 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <4 x i64>, <4 x i64> *%p
%2 = shufflevector <4 x i64> %1, <4 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = bitcast <8 x i64> %2 to <16 x i32>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x i32> %3, <16 x i32> zeroinitializer
ret <16 x i32> %res
}
define <4 x double> @test_broadcast_4f32_4f64(<4 x float> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_4f32_4f64:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcastf64x2 {{.*#+}} ymm0 {%k1} {z} = mem[0,1,0,1]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <4 x float>, <4 x float> *%p
%2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = bitcast <8 x float> %2 to <4 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x double> %3, <4 x double> zeroinitializer
ret <4 x double> %res
}
define <4 x i64> @test_broadcast_4i32_4i64(<4 x i32> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_4i32_4i64:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcasti64x2 {{.*#+}} ymm0 {%k1} {z} = mem[0,1,0,1]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <4 x i32>, <4 x i32> *%p
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = bitcast <8 x i32> %2 to <4 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i64> %3, <4 x i64> zeroinitializer
ret <4 x i64> %res
}
define <8 x double> @test_broadcast_4f32_8f64(<4 x float> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_4f32_8f64:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcastf64x2 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,0,1,0,1,0,1]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <4 x float>, <4 x float> *%p
%2 = shufflevector <4 x float> %1, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = bitcast <16 x float> %2 to <8 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x double> %3, <8 x double> zeroinitializer
ret <8 x double> %res
}
define <8 x i64> @test_broadcast_4i32_8i64(<4 x i32> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_4i32_8i64:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcasti64x2 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,0,1,0,1,0,1]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <4 x i32>, <4 x i32> *%p
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = bitcast <16 x i32> %2 to <8 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i64> %3, <8 x i64> zeroinitializer
ret <8 x i64> %res
}
define <8 x double> @test_broadcast_8f32_8f64(<8 x float> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_8f32_8f64:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcastf64x4 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,2,3,0,1,2,3]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <8 x float>, <8 x float> *%p
%2 = shufflevector <8 x float> %1, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = bitcast <16 x float> %2 to <8 x double>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x double> %3, <8 x double> zeroinitializer
ret <8 x double> %res
}
define <8 x i64> @test_broadcast_8i32_8i64(<8 x i32> *%p, i8 %mask) nounwind {
; CHECK-LABEL: test_broadcast_8i32_8i64:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %esi, %k1
[AVX-512] Add support for taking a bitcast between a SUBV_BROADCAST and VSELECT and moving it to the input of the SUBV_BROADCAST if it will help with using a masked operation. llvm-svn: 292201
2017-01-17 14:49:59 +08:00
; CHECK-NEXT: vbroadcasti64x4 {{.*#+}} zmm0 {%k1} {z} = mem[0,1,2,3,0,1,2,3]
[AVX-512] Add test cases showing missed opportunities to fold subvector broadcasts with a mask operation. llvm-svn: 292200
2017-01-17 14:49:54 +08:00
; CHECK-NEXT: retq
%1 = load <8 x i32>, <8 x i32> *%p
%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = bitcast <16 x i32> %2 to <8 x i64>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i64> %3, <8 x i64> zeroinitializer
ret <8 x i64> %res
}
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
define <4 x float> @test_broadcastf32x2_v4f32(<4 x float> %vec, <4 x float> %passthru, i8 %mask) {
; CHECK-LABEL: test_broadcastf32x2_v4f32:
; CHECK: # BB#0:
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
; CHECK-NEXT: retq
%shuf = shufflevector <4 x float> %vec, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuf, <4 x float> %passthru
ret <4 x float> %res
}
define <4 x float> @test_broadcastf32x2_v4f32_z(<4 x float> %vec, i8 %mask) {
; CHECK-LABEL: test_broadcastf32x2_v4f32_z:
; CHECK: # BB#0:
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vmovaps %xmm0, %xmm0 {%k1} {z}
; CHECK-NEXT: retq
%shuf = shufflevector <4 x float> %vec, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x float> %shuf, <4 x float> zeroinitializer
ret <4 x float> %res
}
define <4 x i32> @test_broadcasti32x2_v4i32(<4 x i32> %vec, <4 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: test_broadcasti32x2_v4i32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[X86] Add 128-bit version of vbroadcasti32x2 to shuffle comment decoding. llvm-svn: 315395
2017-10-11 08:11:53 +08:00
; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} xmm1 {%k1} = xmm0[0,1,0,1]
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vmovdqa %xmm1, %xmm0
; CHECK-NEXT: retq
%shuf = shufflevector <4 x i32> %vec, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuf, <4 x i32> %passthru
ret <4 x i32> %res
}
define <4 x i32> @test_broadcasti32x2_v4i32_z(<4 x i32> %vec, i8 %mask) {
; CHECK-LABEL: test_broadcasti32x2_v4i32_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[X86] Add 128-bit version of vbroadcasti32x2 to shuffle comment decoding. llvm-svn: 315395
2017-10-11 08:11:53 +08:00
; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} xmm0 {%k1} {z} = xmm0[0,1,0,1]
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: retq
%shuf = shufflevector <4 x i32> %vec, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = select <4 x i1> %mask.extract, <4 x i32> %shuf, <4 x i32> zeroinitializer
ret <4 x i32> %res
}
define <8 x float> @test_broadcastf32x2_v8f32(<8 x float> %vec, <8 x float> %passthru, i8 %mask) {
; CHECK-LABEL: test_broadcastf32x2_v8f32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} ymm1 {%k1} = xmm0[0,1,0,1,0,1,0,1]
; CHECK-NEXT: vmovapd %ymm1, %ymm0
; CHECK-NEXT: retq
%shuf = shufflevector <8 x float> %vec, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuf, <8 x float> %passthru
ret <8 x float> %res
}
define <8 x float> @test_broadcastf32x2_v8f32_z(<8 x float> %vec, i8 %mask) {
; CHECK-LABEL: test_broadcastf32x2_v8f32_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} ymm0 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1]
; CHECK-NEXT: retq
%shuf = shufflevector <8 x float> %vec, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x float> %shuf, <8 x float> zeroinitializer
ret <8 x float> %res
}
define <8 x i32> @test_broadcasti32x2_v8i32(<8 x i32> %vec, <8 x i32> %passthru, i8 %mask) {
; CHECK-LABEL: test_broadcasti32x2_v8i32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} ymm1 {%k1} = xmm0[0,1,0,1,0,1,0,1]
; CHECK-NEXT: vmovdqa %ymm1, %ymm0
; CHECK-NEXT: retq
%shuf = shufflevector <8 x i32> %vec, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuf, <8 x i32> %passthru
ret <8 x i32> %res
}
define <8 x i32> @test_broadcasti32x2_v8i32_z(<8 x i32> %vec, i8 %mask) {
; CHECK-LABEL: test_broadcasti32x2_v8i32_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} ymm0 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1]
; CHECK-NEXT: retq
%shuf = shufflevector <8 x i32> %vec, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i8 %mask to <8 x i1>
%res = select <8 x i1> %mask.cast, <8 x i32> %shuf, <8 x i32> zeroinitializer
ret <8 x i32> %res
}
define <16 x float> @test_broadcastf32x2_v16f32_z(<16 x float> %vec, i16 %mask) {
; CHECK-LABEL: test_broadcastf32x2_v16f32_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} zmm0 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
; CHECK-NEXT: retq
%shuf = shufflevector <16 x float> %vec, <16 x float> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x float> %shuf, <16 x float> zeroinitializer
ret <16 x float> %res
}
define <16 x i32> @test_broadcasti32x2_v16i32(<16 x i32> %vec, <16 x i32> %passthru, i16 %mask) {
; CHECK-LABEL: test_broadcasti32x2_v16i32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} zmm1 {%k1} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf = shufflevector <16 x i32> %vec, <16 x i32> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x i32> %shuf, <16 x i32> %passthru
ret <16 x i32> %res
}
define <16 x float> @test_broadcastf32x2_v16f32(<16 x float> %vec, <16 x float> %passthru, i16 %mask) {
; CHECK-LABEL: test_broadcastf32x2_v16f32:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcastf32x2 {{.*#+}} zmm1 {%k1} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
; CHECK-NEXT: vmovapd %zmm1, %zmm0
; CHECK-NEXT: retq
%shuf = shufflevector <16 x float> %vec, <16 x float> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x float> %shuf, <16 x float> %passthru
ret <16 x float> %res
}
define <16 x i32> @test_broadcasti32x2_v16i32_z(<16 x i32> %vec, i16 %mask) {
; CHECK-LABEL: test_broadcasti32x2_v16i32_z:
; CHECK: # BB#0:
[X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an upcoming commit. llvm-svn: 315970
2017-10-17 12:17:55 +08:00
; CHECK-NEXT: kmovd %edi, %k1
[AVX512] Correct isel patterns to support selecting masked vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
2017-08-30 15:48:39 +08:00
; CHECK-NEXT: vbroadcasti32x2 {{.*#+}} zmm0 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
; CHECK-NEXT: retq
%shuf = shufflevector <16 x i32> %vec, <16 x i32> undef, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
%mask.cast = bitcast i16 %mask to <16 x i1>
%res = select <16 x i1> %mask.cast, <16 x i32> %shuf, <16 x i32> zeroinitializer
ret <16 x i32> %res
}