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llvm-project/llvm/test/CodeGen/X86/sbb.ll

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[x86] add tests for select --> sbb transform; NFC llvm-svn: 306032
2017-06-23 01:01:14 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; Vary the operand sizes for extra coverage, but the transform should be identical in all cases.
; (X == 0) ? 0 : -1 --> (X == 0) - 1
define i8 @i8_select_0_or_neg1(i8 %x) {
; CHECK-LABEL: i8_select_0_or_neg1:
; CHECK: # BB#0:
[x86] add/sub (X==0) --> sbb(neg X) Our handling of select-of-constants is lumpy in IR (https://reviews.llvm.org/D24480), lumpy in DAGCombiner, and lumpy in X86ISelLowering. That's why we only had the 'sbb' codegen in 1 out of the 4 tests. This is a step towards smoothing that out. First, show that all of these IR forms are equivalent: http://rise4fun.com/Alive/mx Second, show that the 'sbb' version is faster/smaller. IACA output for SandyBridge (later Intel and AMD chips are similar based on Agner's tables): This is the "obvious" x86 codegen (what gcc appears to produce currently): | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | test edi, edi | 1 | | | | | | 1.0 | CP | setnz al | 1 | | 1.0 | | | | | CP | neg eax This is the adc version: | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | adc eax, 0xffffffff And this is sbb: | 1 | 1.0 | | | | | | | neg edi | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax If IACA is trustworthy, then sbb became a single uop in Broadwell, so this will be clearly better than the alternatives going forward. llvm-svn: 306040
2017-06-23 02:11:19 +08:00
; CHECK-NEXT: negb %dil
; CHECK-NEXT: sbbb %al, %al
[x86] add tests for select --> sbb transform; NFC llvm-svn: 306032
2017-06-23 01:01:14 +08:00
; CHECK-NEXT: retq
%cmp = icmp eq i8 %x, 0
%sel = select i1 %cmp, i8 0, i8 -1
ret i8 %sel
}
; (X == 0) ? 0 : -1 --> (X == 0) - 1
define i16 @i16_select_0_or_neg1_as_math(i16 %x) {
; CHECK-LABEL: i16_select_0_or_neg1_as_math:
; CHECK: # BB#0:
[x86] add/sub (X==0) --> sbb(neg X) Our handling of select-of-constants is lumpy in IR (https://reviews.llvm.org/D24480), lumpy in DAGCombiner, and lumpy in X86ISelLowering. That's why we only had the 'sbb' codegen in 1 out of the 4 tests. This is a step towards smoothing that out. First, show that all of these IR forms are equivalent: http://rise4fun.com/Alive/mx Second, show that the 'sbb' version is faster/smaller. IACA output for SandyBridge (later Intel and AMD chips are similar based on Agner's tables): This is the "obvious" x86 codegen (what gcc appears to produce currently): | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | test edi, edi | 1 | | | | | | 1.0 | CP | setnz al | 1 | | 1.0 | | | | | CP | neg eax This is the adc version: | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | adc eax, 0xffffffff And this is sbb: | 1 | 1.0 | | | | | | | neg edi | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax If IACA is trustworthy, then sbb became a single uop in Broadwell, so this will be clearly better than the alternatives going forward. llvm-svn: 306040
2017-06-23 02:11:19 +08:00
; CHECK-NEXT: negw %di
; CHECK-NEXT: sbbw %ax, %ax
[x86] add tests for select --> sbb transform; NFC llvm-svn: 306032
2017-06-23 01:01:14 +08:00
; CHECK-NEXT: retq
%cmp = icmp eq i16 %x, 0
%ext = zext i1 %cmp to i16
%add = add i16 %ext, -1
ret i16 %add
}
[x86] add more tests for select --> sbb transform; NFC These are siblings of the tests added with r306032. llvm-svn: 306064
2017-06-23 06:17:05 +08:00
; (X != 0) ? -1 : 0 --> 0 - (X != 0)
[x86] add tests for select --> sbb transform; NFC llvm-svn: 306032
2017-06-23 01:01:14 +08:00
define i32 @i32_select_0_or_neg1_commuted(i32 %x) {
; CHECK-LABEL: i32_select_0_or_neg1_commuted:
; CHECK: # BB#0:
; CHECK-NEXT: negl %edi
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: retq
%cmp = icmp ne i32 %x, 0
%sel = select i1 %cmp, i32 -1, i32 0
ret i32 %sel
}
[x86] add more tests for select --> sbb transform; NFC These are siblings of the tests added with r306032. llvm-svn: 306064
2017-06-23 06:17:05 +08:00
; (X != 0) ? -1 : 0 --> 0 - (X != 0)
[x86] add tests for select --> sbb transform; NFC llvm-svn: 306032
2017-06-23 01:01:14 +08:00
define i64 @i64_select_0_or_neg1_commuted_as_math(i64 %x) {
; CHECK-LABEL: i64_select_0_or_neg1_commuted_as_math:
; CHECK: # BB#0:
[x86] add/sub (X==0) --> sbb(neg X) Our handling of select-of-constants is lumpy in IR (https://reviews.llvm.org/D24480), lumpy in DAGCombiner, and lumpy in X86ISelLowering. That's why we only had the 'sbb' codegen in 1 out of the 4 tests. This is a step towards smoothing that out. First, show that all of these IR forms are equivalent: http://rise4fun.com/Alive/mx Second, show that the 'sbb' version is faster/smaller. IACA output for SandyBridge (later Intel and AMD chips are similar based on Agner's tables): This is the "obvious" x86 codegen (what gcc appears to produce currently): | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | test edi, edi | 1 | | | | | | 1.0 | CP | setnz al | 1 | | 1.0 | | | | | CP | neg eax This is the adc version: | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | adc eax, 0xffffffff And this is sbb: | 1 | 1.0 | | | | | | | neg edi | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax If IACA is trustworthy, then sbb became a single uop in Broadwell, so this will be clearly better than the alternatives going forward. llvm-svn: 306040
2017-06-23 02:11:19 +08:00
; CHECK-NEXT: negq %rdi
; CHECK-NEXT: sbbq %rax, %rax
[x86] add tests for select --> sbb transform; NFC llvm-svn: 306032
2017-06-23 01:01:14 +08:00
; CHECK-NEXT: retq
%cmp = icmp ne i64 %x, 0
%ext = zext i1 %cmp to i64
[x86] add more tests for select --> sbb transform; NFC These are siblings of the tests added with r306032. llvm-svn: 306064
2017-06-23 06:17:05 +08:00
%sub = sub i64 0, %ext
ret i64 %sub
}
; (X == 0) ? -1 : 0 --> 0 - (X == 0)
define i64 @i64_select_neg1_or_0(i64 %x) {
; CHECK-LABEL: i64_select_neg1_or_0:
; CHECK: # BB#0:
; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: sbbq %rax, %rax
; CHECK-NEXT: retq
%cmp = icmp eq i64 %x, 0
%sel = select i1 %cmp, i64 -1, i64 0
ret i64 %sel
}
; (X == 0) ? -1 : 0 --> 0 - (X == 0)
define i32 @i32_select_neg1_or_0_as_math(i32 %x) {
; CHECK-LABEL: i32_select_neg1_or_0_as_math:
; CHECK: # BB#0:
; CHECK-NEXT: cmpl $1, %edi
[x86] add/sub (X==0) --> sbb(cmp X, 1) This is very similar to the transform in: https://reviews.llvm.org/rL306040 ...but in this case, we use cmp X, 1 to set the carry bit as needed. Again, we can show that all of these are logically equivalent (although InstCombine currently canonicalizes to a form not seen here), and if we believe IACA, then this is the smallest/fastest code. Eg, with SNB: | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1 | 1.0 | | | | | | | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax The larger motivation is to clean up all select-of-constants combining/lowering because we're missing some common cases. llvm-svn: 306072
2017-06-23 07:47:15 +08:00
; CHECK-NEXT: sbbl %eax, %eax
[x86] add more tests for select --> sbb transform; NFC These are siblings of the tests added with r306032. llvm-svn: 306064
2017-06-23 06:17:05 +08:00
; CHECK-NEXT: retq
%cmp = icmp eq i32 %x, 0
%ext = zext i1 %cmp to i32
%sub = sub i32 0, %ext
ret i32 %sub
}
; (X != 0) ? 0 : -1 --> (X != 0) - 1
define i16 @i16_select_neg1_or_0_commuted(i16 %x) {
; CHECK-LABEL: i16_select_neg1_or_0_commuted:
; CHECK: # BB#0:
; CHECK-NEXT: cmpw $1, %di
[x86] add/sub (X==0) --> sbb(cmp X, 1) This is very similar to the transform in: https://reviews.llvm.org/rL306040 ...but in this case, we use cmp X, 1 to set the carry bit as needed. Again, we can show that all of these are logically equivalent (although InstCombine currently canonicalizes to a form not seen here), and if we believe IACA, then this is the smallest/fastest code. Eg, with SNB: | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1 | 1.0 | | | | | | | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax The larger motivation is to clean up all select-of-constants combining/lowering because we're missing some common cases. llvm-svn: 306072
2017-06-23 07:47:15 +08:00
; CHECK-NEXT: sbbw %ax, %ax
[x86] add more tests for select --> sbb transform; NFC These are siblings of the tests added with r306032. llvm-svn: 306064
2017-06-23 06:17:05 +08:00
; CHECK-NEXT: retq
%cmp = icmp ne i16 %x, 0
%sel = select i1 %cmp, i16 0, i16 -1
ret i16 %sel
}
; (X != 0) ? 0 : -1 --> (X != 0) - 1
define i8 @i8_select_neg1_or_0_commuted_as_math(i8 %x) {
; CHECK-LABEL: i8_select_neg1_or_0_commuted_as_math:
; CHECK: # BB#0:
; CHECK-NEXT: cmpb $1, %dil
[x86] add/sub (X==0) --> sbb(cmp X, 1) This is very similar to the transform in: https://reviews.llvm.org/rL306040 ...but in this case, we use cmp X, 1 to set the carry bit as needed. Again, we can show that all of these are logically equivalent (although InstCombine currently canonicalizes to a form not seen here), and if we believe IACA, then this is the smallest/fastest code. Eg, with SNB: | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1 | 1.0 | | | | | | | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax The larger motivation is to clean up all select-of-constants combining/lowering because we're missing some common cases. llvm-svn: 306072
2017-06-23 07:47:15 +08:00
; CHECK-NEXT: sbbb %al, %al
[x86] add more tests for select --> sbb transform; NFC These are siblings of the tests added with r306032. llvm-svn: 306064
2017-06-23 06:17:05 +08:00
; CHECK-NEXT: retq
%cmp = icmp ne i8 %x, 0
%ext = zext i1 %cmp to i8
%add = add i8 %ext, -1
ret i8 %add
[x86] add tests for select --> sbb transform; NFC llvm-svn: 306032
2017-06-23 01:01:14 +08:00
}