maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_ldnt1uh.c

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

260 lines
19 KiB
C
Raw Normal View History

[AArch64][SVE] Enable __ARM_FEATURE_SVE macros. This patch enables the following macros when their corresponding target attributes are set: __ARM_FEATURE_SVE (+sve) __ARM_FEATURE_SVE2 (+sve2) __ARM_FEATURE_SVE2_AES (+sve2-aes) __ARM_FEATURE_SVE2_BITPERM (+sve2-bitperm) __ARM_FEATURE_SVE2_SHA3 (+sve2-sha3) __ARM_FEATURE_SVE2_SM4 (+sve2-sm4) This implies that the base SVE and SVE2 ACLE (00bet2) are now feature complete, meaning that all intrinsics are implemented in LLVM and Clang. Disclaimer: To implement the ACLE we have had to fix up many parts of LLVM to make it support scalable vectors. We have also used many target-specific intrinsics to reduce reliance on parts of LLVM where we know scalable vectors may not yet be handled properly (e.g. some transformation might drop the 'scalable' flag on a vector type). While we've done a best effort with the limited testing that is available to us, we're still working to improve the stability of the implementation. Additionally, Clang may print warnings that code may have miscompiled. We find this often to be a false alarm where the wrong interfaces have been used in LLVM and where resulting code is not actually incorrect. However, this warrants a bug report and investigation. If you find any bugs or issues, please raise them on bugs.llvm.org and let us know! Reviewers: rengolin, efriedma, david-arm, SjoerdMeijer Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D81725
2020-06-24 23:52:41 +08:00
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
[SveEmitter] Implement builtins for gathers/scatters This patch adds builtins for: * regular, first-faulting and non-temporal gather loads * regular and non-temporal scatter stores Differential Revision: https://reviews.llvm.org/D77735
2020-04-07 18:09:01 +08:00
#include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
#else
#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
#endif
svint32_t test_svldnt1uh_gather_u32base_s32(svbool_t pg, svuint32_t bases) {
// CHECK-LABEL: test_svldnt1uh_gather_u32base_s32
// CHECK: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> %bases, i64 0)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_s32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_s32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _s32, )(pg, bases);
}
svint64_t test_svldnt1uh_gather_u64base_s64(svbool_t pg, svuint64_t bases) {
// CHECK-LABEL: test_svldnt1uh_gather_u64base_s64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> %bases, i64 0)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_s64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_s64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _s64, )(pg, bases);
}
svuint32_t test_svldnt1uh_gather_u32base_u32(svbool_t pg, svuint32_t bases) {
// CHECK-LABEL: test_svldnt1uh_gather_u32base_u32
// CHECK: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> %bases, i64 0)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_u32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_u32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _u32, )(pg, bases);
}
svuint64_t test_svldnt1uh_gather_u64base_u64(svbool_t pg, svuint64_t bases) {
// CHECK-LABEL: test_svldnt1uh_gather_u64base_u64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> %bases, i64 0)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_u64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_u64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _u64, )(pg, bases);
}
svint64_t test_svldnt1uh_gather_s64offset_s64(svbool_t pg, const uint16_t *base, svint64_t offsets) {
// CHECK-LABEL: test_svldnt1uh_gather_s64offset_s64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %offsets)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64offset_s64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, offset_s64, )(pg, base, offsets);
}
svuint64_t test_svldnt1uh_gather_s64offset_u64(svbool_t pg, const uint16_t *base, svint64_t offsets) {
// CHECK-LABEL: test_svldnt1uh_gather_s64offset_u64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %offsets)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64offset_u64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, offset_u64, )(pg, base, offsets);
}
svint32_t test_svldnt1uh_gather_u32offset_s32(svbool_t pg, const uint16_t *base, svuint32_t offsets) {
// CHECK-LABEL: test_svldnt1uh_gather_u32offset_s32
// CHECK: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16(<vscale x 4 x i1> [[PG]], i16* %base, <vscale x 4 x i32> %offsets)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32offset_s32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, u32, offset_s32, )(pg, base, offsets);
}
svint64_t test_svldnt1uh_gather_u64offset_s64(svbool_t pg, const uint16_t *base, svuint64_t offsets) {
// CHECK-LABEL: test_svldnt1uh_gather_u64offset_s64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %offsets)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64offset_s64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, offset_s64, )(pg, base, offsets);
}
svuint32_t test_svldnt1uh_gather_u32offset_u32(svbool_t pg, const uint16_t *base, svuint32_t offsets) {
// CHECK-LABEL: test_svldnt1uh_gather_u32offset_u32
// CHECK: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.uxtw.nxv4i16(<vscale x 4 x i1> [[PG]], i16* %base, <vscale x 4 x i32> %offsets)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32offset_u32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, u32, offset_u32, )(pg, base, offsets);
}
svuint64_t test_svldnt1uh_gather_u64offset_u64(svbool_t pg, const uint16_t *base, svuint64_t offsets) {
// CHECK-LABEL: test_svldnt1uh_gather_u64offset_u64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %offsets)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64offset_u64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, offset_u64, )(pg, base, offsets);
}
svint32_t test_svldnt1uh_gather_u32base_offset_s32(svbool_t pg, svuint32_t bases, int64_t offset) {
// CHECK-LABEL: test_svldnt1uh_gather_u32base_offset_s32
// CHECK: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> %bases, i64 %offset)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_offset_s32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _offset_s32, )(pg, bases, offset);
}
svint64_t test_svldnt1uh_gather_u64base_offset_s64(svbool_t pg, svuint64_t bases, int64_t offset) {
// CHECK-LABEL: test_svldnt1uh_gather_u64base_offset_s64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> %bases, i64 %offset)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_s64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_offset_s64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _offset_s64, )(pg, bases, offset);
}
svuint32_t test_svldnt1uh_gather_u32base_offset_u32(svbool_t pg, svuint32_t bases, int64_t offset) {
// CHECK-LABEL: test_svldnt1uh_gather_u32base_offset_u32
// CHECK: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> %bases, i64 %offset)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_offset_u32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _offset_u32, )(pg, bases, offset);
}
svuint64_t test_svldnt1uh_gather_u64base_offset_u64(svbool_t pg, svuint64_t bases, int64_t offset) {
// CHECK-LABEL: test_svldnt1uh_gather_u64base_offset_u64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> %bases, i64 %offset)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_offset_u64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_offset_u64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _offset_u64, )(pg, bases, offset);
}
svint64_t test_svldnt1uh_gather_s64index_s64(svbool_t pg, const uint16_t *base, svint64_t indices) {
// CHECK-LABEL: test_svldnt1uh_gather_s64index_s64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %indices)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64index_s64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, index_s64, )(pg, base, indices);
}
svuint64_t test_svldnt1uh_gather_s64index_u64(svbool_t pg, const uint16_t *base, svint64_t indices) {
// CHECK-LABEL: test_svldnt1uh_gather_s64index_u64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %indices)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_s64index_u64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, s64, index_u64, )(pg, base, indices);
}
svint64_t test_svldnt1uh_gather_u64index_s64(svbool_t pg, const uint16_t *base, svuint64_t indices) {
// CHECK-LABEL: test_svldnt1uh_gather_u64index_s64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %indices)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64index_s64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, index_s64, )(pg, base, indices);
}
svuint64_t test_svldnt1uh_gather_u64index_u64(svbool_t pg, const uint16_t *base, svuint64_t indices) {
// CHECK-LABEL: test_svldnt1uh_gather_u64index_u64
// CHECK: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.index.nxv2i16(<vscale x 2 x i1> [[PG]], i16* %base, <vscale x 2 x i64> %indices)
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64index_u64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather_, u64, index_u64, )(pg, base, indices);
}
svint32_t test_svldnt1uh_gather_u32base_index_s32(svbool_t pg, svuint32_t bases, int64_t index) {
// CHECK-LABEL: test_svldnt1uh_gather_u32base_index_s32
// CHECK-DAG: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> %bases, i64 [[SHL]])
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_index_s32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _index_s32, )(pg, bases, index);
}
svint64_t test_svldnt1uh_gather_u64base_index_s64(svbool_t pg, svuint64_t bases, int64_t index) {
// CHECK-LABEL: test_svldnt1uh_gather_u64base_index_s64
// CHECK-DAG: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> %bases, i64 [[SHL]])
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_s64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_index_s64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _index_s64, )(pg, bases, index);
}
svuint32_t test_svldnt1uh_gather_u32base_index_u32(svbool_t pg, svuint32_t bases, int64_t index) {
// CHECK-LABEL: test_svldnt1uh_gather_u32base_index_u32
// CHECK-DAG: [[PG:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1
// CHECK: [[LOAD:%.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv4i16.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> %bases, i64 [[SHL]])
// CHECK: [[ZEXT:%.*]] = zext <vscale x 4 x i16> [[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u32'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u32base_index_u32'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u32base, _index_u32, )(pg, bases, index);
}
svuint64_t test_svldnt1uh_gather_u64base_index_u64(svbool_t pg, svuint64_t bases, int64_t index) {
// CHECK-LABEL: test_svldnt1uh_gather_u64base_index_u64
// CHECK-DAG: [[PG:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: [[SHL:%.*]] = shl i64 %index, 1
// CHECK: [[LOAD:%.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnt1.gather.scalar.offset.nxv2i16.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> %bases, i64 [[SHL]])
// CHECK: [[ZEXT:%.*]] = zext <vscale x 2 x i16> [[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> [[ZEXT]]
// overload-warning@+2 {{implicit declaration of function 'svldnt1uh_gather_index_u64'}}
// expected-warning@+1 {{implicit declaration of function 'svldnt1uh_gather_u64base_index_u64'}}
return SVE_ACLE_FUNC(svldnt1uh_gather, _u64base, _index_u64, )(pg, bases, index);
}