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llvm-project/llvm/test/CodeGen/X86/pr34177.ll

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[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mattr=+avx512f | FileCheck %s
; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define void @test() local_unnamed_addr {
; CHECK-LABEL: test:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,3]
; CHECK-NEXT: vpextrq $1, %xmm0, %rax
; CHECK-NEXT: vmovq %xmm0, %rcx
; CHECK-NEXT: negq %rdx
; CHECK-NEXT: fld1
; CHECK-NEXT: fldz
; CHECK-NEXT: fld %st(0)
; CHECK-NEXT: fcmove %st(2), %st(0)
; CHECK-NEXT: cmpq %rax, %rcx
; CHECK-NEXT: fld %st(1)
; CHECK-NEXT: fcmove %st(3), %st(0)
; CHECK-NEXT: cmpq %rax, %rax
; CHECK-NEXT: fld %st(2)
; CHECK-NEXT: fcmove %st(4), %st(0)
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: cmpq %rax, %rax
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
; CHECK-NEXT: fxch %st(3)
; CHECK-NEXT: fcmove %st(4), %st(0)
; CHECK-NEXT: fstp %st(4)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fadd %st(0), %st(0)
; CHECK-NEXT: fxch %st(3)
; CHECK-NEXT: fadd %st(0), %st(0)
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: fxch %st(2)
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
; CHECK-NEXT: fadd %st(0), %st(0)
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: fxch %st(1)
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
; CHECK-NEXT: fadd %st(0), %st(0)
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: fxch %st(3)
; CHECK-NEXT: fstpt (%rax)
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
; CHECK-NEXT: fxch %st(2)
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: fstpt (%rax)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fstpt (%rax)
; CHECK-NEXT: fstpt (%rax)
%1 = icmp eq <4 x i64> <i64 0, i64 1, i64 2, i64 3>, undef
%2 = select <4 x i1> %1, <4 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000>, <4 x x86_fp80> zeroinitializer
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
%3 = fadd <4 x x86_fp80> %2, %2
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
%4 = shufflevector <4 x x86_fp80> %3, <4 x x86_fp80> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x x86_fp80> %4, <8 x x86_fp80>* undef, align 16
unreachable
}