2014-05-24 20:50:23 +08:00
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//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
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2014-03-29 18:18:08 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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2014-05-24 20:50:23 +08:00
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#include "AArch64.h"
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2016-04-07 01:26:03 +08:00
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#include "AArch64CallLowering.h"
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2016-07-27 22:31:55 +08:00
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#include "AArch64InstructionSelector.h"
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2016-10-15 06:18:18 +08:00
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#include "AArch64LegalizerInfo.h"
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2017-02-01 10:54:34 +08:00
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#include "AArch64MacroFusion.h"
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Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 19:15:55 +08:00
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#ifdef LLVM_BUILD_GLOBAL_ISEL
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2016-04-07 01:26:03 +08:00
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#include "AArch64RegisterBankInfo.h"
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Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 19:15:55 +08:00
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#endif
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2017-01-06 08:30:53 +08:00
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#include "AArch64Subtarget.h"
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2014-05-24 20:50:23 +08:00
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#include "AArch64TargetMachine.h"
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2014-11-13 17:26:31 +08:00
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#include "AArch64TargetObjectFile.h"
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2015-01-31 19:17:59 +08:00
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#include "AArch64TargetTransformInfo.h"
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2017-01-06 08:30:53 +08:00
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
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2016-04-08 05:24:40 +08:00
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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2016-07-27 22:31:55 +08:00
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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2016-10-15 06:18:18 +08:00
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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2016-04-08 04:27:33 +08:00
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#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
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2016-11-29 04:11:54 +08:00
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#include "llvm/CodeGen/MachineScheduler.h"
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2014-03-29 18:18:08 +08:00
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#include "llvm/CodeGen/Passes.h"
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2016-05-10 11:21:59 +08:00
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#include "llvm/CodeGen/TargetPassConfig.h"
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2017-01-06 08:30:53 +08:00
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#include "llvm/IR/Attributes.h"
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2014-10-06 14:45:36 +08:00
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#include "llvm/IR/Function.h"
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2017-01-06 08:30:53 +08:00
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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2014-03-29 18:18:08 +08:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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2017-01-06 08:30:53 +08:00
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#include "llvm/Target/TargetLoweringObjectFile.h"
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2014-03-29 18:18:08 +08:00
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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2017-01-06 08:30:53 +08:00
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#include <memory>
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#include <string>
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2014-03-29 18:18:08 +08:00
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using namespace llvm;
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2016-08-01 13:56:57 +08:00
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static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
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cl::desc("Enable the CCMP formation pass"),
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cl::init(true), cl::Hidden);
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2014-05-08 00:41:55 +08:00
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2016-08-01 13:56:57 +08:00
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static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
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2014-08-08 05:40:58 +08:00
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cl::desc("Enable the machine combiner pass"),
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cl::init(true), cl::Hidden);
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2016-08-01 13:56:57 +08:00
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static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
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cl::desc("Suppress STP for AArch64"),
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cl::init(true), cl::Hidden);
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2014-03-29 18:18:08 +08:00
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2016-08-01 13:56:57 +08:00
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static cl::opt<bool> EnableAdvSIMDScalar(
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"aarch64-enable-simd-scalar",
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cl::desc("Enable use of AdvSIMD scalar integer instructions"),
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cl::init(false), cl::Hidden);
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2014-03-29 18:18:08 +08:00
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2014-04-15 05:05:02 +08:00
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static cl::opt<bool>
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2016-08-01 13:56:57 +08:00
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EnablePromoteConstant("aarch64-enable-promote-const",
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cl::desc("Enable the promote constant pass"),
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cl::init(true), cl::Hidden);
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2014-04-15 05:05:02 +08:00
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2016-08-01 13:56:57 +08:00
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static cl::opt<bool> EnableCollectLOH(
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"aarch64-enable-collect-loh",
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cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
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cl::init(true), cl::Hidden);
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[AArch64] Add pass to remove redundant copy after RA
Summary:
This change will add a pass to remove unnecessary zero copies in target blocks
of cbz/cbnz instructions. E.g., the copy instruction in the code below can be
removed because the cbz jumps to BB1 when x0 is zero :
BB0:
cbz x0, .BB1
BB1:
mov x0, xzr
Jun
Reviewers: gberry, jmolloy, HaoLiu, MatzeB, mcrosier
Subscribers: mcrosier, mssimpso, haicheng, bmakam, llvm-commits, aemerson, rengolin
Differential Revision: http://reviews.llvm.org/D16203
llvm-svn: 261004
2016-02-17 04:02:39 +08:00
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2014-05-08 00:41:55 +08:00
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static cl::opt<bool>
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2016-08-01 13:56:57 +08:00
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EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
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cl::desc("Enable the pass that removes dead"
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" definitons and replaces stores to"
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" them with stores to the zero"
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" register"),
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cl::init(true));
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static cl::opt<bool> EnableRedundantCopyElimination(
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"aarch64-enable-copyelim",
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cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
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cl::Hidden);
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static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
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cl::desc("Enable the load/store pair"
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" optimization pass"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool> EnableAtomicTidy(
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"aarch64-enable-atomic-cfg-tidy", cl::Hidden,
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cl::desc("Run SimplifyCFG after expanding atomic operations"
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" to make use of cmpxchg flow-based information"),
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cl::init(true));
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2014-05-30 18:09:59 +08:00
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2014-08-06 21:31:32 +08:00
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static cl::opt<bool>
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EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
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cl::desc("Run early if-conversion"),
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cl::init(true));
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2014-09-05 10:55:24 +08:00
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static cl::opt<bool>
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2016-08-01 13:56:57 +08:00
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EnableCondOpt("aarch64-enable-condopt",
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cl::desc("Enable the condition optimizer pass"),
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cl::init(true), cl::Hidden);
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2014-09-05 10:55:24 +08:00
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2014-10-13 18:12:35 +08:00
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static cl::opt<bool>
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EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
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cl::desc("Work around Cortex-A53 erratum 835769"),
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cl::init(false));
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2014-11-19 14:39:53 +08:00
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static cl::opt<bool>
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2016-08-01 13:56:57 +08:00
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EnableAddressTypePromotion("aarch64-enable-type-promotion", cl::Hidden,
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cl::desc("Enable the type promotion pass"),
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cl::init(true));
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static cl::opt<bool>
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EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
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cl::desc("Enable optimizations on complex GEPs"),
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cl::init(false));
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static cl::opt<bool>
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BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
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cl::desc("Relax out of range conditional branches"));
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2014-11-19 14:39:53 +08:00
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2015-04-11 08:06:36 +08:00
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// FIXME: Unify control over GlobalMerge.
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static cl::opt<cl::boolOrDefault>
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2016-08-01 13:56:57 +08:00
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EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
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cl::desc("Enable the global merge pass"));
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2015-04-11 08:06:36 +08:00
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2016-03-18 08:27:29 +08:00
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static cl::opt<bool>
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2016-08-01 13:56:57 +08:00
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EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
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2016-03-18 08:27:29 +08:00
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cl::desc("Enable the loop data prefetch pass"),
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2016-03-30 08:21:29 +08:00
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cl::init(true));
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2016-03-18 08:27:29 +08:00
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2017-03-02 07:33:08 +08:00
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static cl::opt<int> EnableGlobalISelAtO(
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"aarch64-enable-global-isel-at-O", cl::Hidden,
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cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
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cl::init(-1));
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2014-05-24 20:50:23 +08:00
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extern "C" void LLVMInitializeAArch64Target() {
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2014-03-29 18:18:08 +08:00
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// Register the target.
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2016-10-10 07:00:34 +08:00
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RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
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RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
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RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
|
2016-04-02 07:14:52 +08:00
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auto PR = PassRegistry::getPassRegistry();
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initializeGlobalISel(*PR);
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2016-08-01 13:56:57 +08:00
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initializeAArch64A53Fix835769Pass(*PR);
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initializeAArch64A57FPLoadBalancingPass(*PR);
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initializeAArch64AddressTypePromotionPass(*PR);
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initializeAArch64AdvSIMDScalarPass(*PR);
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initializeAArch64CollectLOHPass(*PR);
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initializeAArch64ConditionalComparesPass(*PR);
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initializeAArch64ConditionOptimizerPass(*PR);
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initializeAArch64DeadRegisterDefinitionsPass(*PR);
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2016-04-02 07:14:52 +08:00
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initializeAArch64ExpandPseudoPass(*PR);
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2016-07-21 05:45:58 +08:00
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initializeAArch64LoadStoreOptPass(*PR);
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2016-10-08 20:30:07 +08:00
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initializeAArch64VectorByElementOptPass(*PR);
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2016-08-01 13:56:57 +08:00
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initializeAArch64PromoteConstantPass(*PR);
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initializeAArch64RedundantCopyEliminationPass(*PR);
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initializeAArch64StorePairSuppressPass(*PR);
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initializeLDTLSCleanupPass(*PR);
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2014-03-29 18:18:08 +08:00
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}
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2014-11-13 17:26:31 +08:00
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//===----------------------------------------------------------------------===//
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// AArch64 Lowering public interface.
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//===----------------------------------------------------------------------===//
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatMachO())
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2017-01-06 08:30:53 +08:00
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return llvm::make_unique<AArch64_MachoTargetObjectFile>();
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2014-11-13 17:26:31 +08:00
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2017-01-06 08:30:53 +08:00
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return llvm::make_unique<AArch64_ELFTargetObjectFile>();
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2014-11-13 17:26:31 +08:00
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}
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2015-03-12 08:07:24 +08:00
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// Helper function to build a DataLayout string
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2016-10-24 21:37:13 +08:00
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static std::string computeDataLayout(const Triple &TT,
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const MCTargetOptions &Options,
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bool LittleEndian) {
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if (Options.getABIName() == "ilp32")
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return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
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2015-06-11 23:34:59 +08:00
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if (TT.isOSBinFormatMachO())
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2015-03-12 08:07:24 +08:00
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return "e-m:o-i64:64-i128:128-n32:64-S128";
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if (LittleEndian)
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2016-07-08 04:02:18 +08:00
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return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
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return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
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2015-03-12 08:07:24 +08:00
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}
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2016-05-19 06:04:49 +08:00
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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Optional<Reloc::Model> RM) {
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// AArch64 Darwin is always PIC.
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if (TT.isOSDarwin())
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return Reloc::PIC_;
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// On ELF platforms the default static relocation model has a smart enough
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// linker to cope with referencing external symbols defined in a shared
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// library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
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if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
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return Reloc::Static;
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return *RM;
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}
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2016-05-19 00:00:24 +08:00
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/// Create an AArch64 architecture model.
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2014-03-29 18:18:08 +08:00
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///
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2016-05-19 06:04:49 +08:00
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AArch64TargetMachine::AArch64TargetMachine(
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const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Optional<Reloc::Model> RM,
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CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian)
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2015-03-12 08:07:24 +08:00
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// This nested ternary is horrible, but DL needs to be properly
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2015-03-13 02:23:01 +08:00
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// initialized before TLInfo is constructed.
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2016-10-24 21:37:13 +08:00
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: LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions,
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LittleEndian),
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TT, CPU, FS, Options,
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getEffectiveRelocModel(TT, RM), CM, OL),
|
2015-06-16 23:44:21 +08:00
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TLOF(createTLOF(getTargetTriple())),
|
2016-09-21 03:02:06 +08:00
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isLittle(LittleEndian) {
|
2014-03-29 18:18:08 +08:00
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initAsmInfo();
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|
}
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2017-01-06 08:30:53 +08:00
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AArch64TargetMachine::~AArch64TargetMachine() = default;
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2014-11-21 07:37:18 +08:00
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2016-04-07 01:26:03 +08:00
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#ifdef LLVM_BUILD_GLOBAL_ISEL
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namespace {
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2017-01-06 08:30:53 +08:00
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2016-04-15 01:45:38 +08:00
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struct AArch64GISelActualAccessor : public GISelAccessor {
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2016-04-07 01:26:03 +08:00
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std::unique_ptr<CallLowering> CallLoweringInfo;
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2016-07-27 22:31:55 +08:00
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std::unique_ptr<InstructionSelector> InstSelector;
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2016-10-15 06:18:18 +08:00
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std::unique_ptr<LegalizerInfo> Legalizer;
|
2016-04-07 01:26:03 +08:00
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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2017-01-06 08:30:53 +08:00
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2016-04-07 01:26:03 +08:00
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const CallLowering *getCallLowering() const override {
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return CallLoweringInfo.get();
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}
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2017-01-06 08:30:53 +08:00
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2016-07-27 22:31:55 +08:00
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const InstructionSelector *getInstructionSelector() const override {
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return InstSelector.get();
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}
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2017-01-06 08:30:53 +08:00
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|
|
2016-12-16 02:45:30 +08:00
|
|
|
const LegalizerInfo *getLegalizerInfo() const override {
|
2016-07-23 15:50:05 +08:00
|
|
|
return Legalizer.get();
|
2016-07-23 04:03:43 +08:00
|
|
|
}
|
2017-01-06 08:30:53 +08:00
|
|
|
|
2016-04-07 01:26:03 +08:00
|
|
|
const RegisterBankInfo *getRegBankInfo() const override {
|
|
|
|
return RegBankInfo.get();
|
|
|
|
}
|
|
|
|
};
|
2017-01-06 08:30:53 +08:00
|
|
|
|
|
|
|
} // end anonymous namespace
|
2016-04-07 01:26:03 +08:00
|
|
|
#endif
|
|
|
|
|
2014-10-06 14:45:36 +08:00
|
|
|
const AArch64Subtarget *
|
|
|
|
AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
|
2015-02-14 10:09:06 +08:00
|
|
|
Attribute CPUAttr = F.getFnAttribute("target-cpu");
|
|
|
|
Attribute FSAttr = F.getFnAttribute("target-features");
|
2014-10-06 14:45:36 +08:00
|
|
|
|
|
|
|
std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
|
|
|
|
? CPUAttr.getValueAsString().str()
|
|
|
|
: TargetCPU;
|
|
|
|
std::string FS = !FSAttr.hasAttribute(Attribute::None)
|
|
|
|
? FSAttr.getValueAsString().str()
|
|
|
|
: TargetFS;
|
|
|
|
|
|
|
|
auto &I = SubtargetMap[CPU + FS];
|
|
|
|
if (!I) {
|
|
|
|
// This needs to be done before we create a new subtarget since any
|
|
|
|
// creation will depend on the TM and the code generation flags on the
|
|
|
|
// function that reside in TargetOptions.
|
|
|
|
resetTargetOptions(F);
|
2015-06-16 23:44:21 +08:00
|
|
|
I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
|
2016-09-21 03:02:06 +08:00
|
|
|
isLittle);
|
2016-04-07 01:26:03 +08:00
|
|
|
#ifndef LLVM_BUILD_GLOBAL_ISEL
|
2016-11-14 18:25:43 +08:00
|
|
|
GISelAccessor *GISel = new GISelAccessor();
|
2016-04-07 01:26:03 +08:00
|
|
|
#else
|
2016-04-15 01:45:38 +08:00
|
|
|
AArch64GISelActualAccessor *GISel =
|
2016-04-07 01:26:03 +08:00
|
|
|
new AArch64GISelActualAccessor();
|
2016-04-15 01:45:38 +08:00
|
|
|
GISel->CallLoweringInfo.reset(
|
2016-04-07 01:26:03 +08:00
|
|
|
new AArch64CallLowering(*I->getTargetLowering()));
|
2016-10-15 06:18:18 +08:00
|
|
|
GISel->Legalizer.reset(new AArch64LegalizerInfo());
|
2016-07-27 22:31:55 +08:00
|
|
|
|
|
|
|
auto *RBI = new AArch64RegisterBankInfo(*I->getRegisterInfo());
|
|
|
|
|
|
|
|
// FIXME: At this point, we can't rely on Subtarget having RBI.
|
|
|
|
// It's awkward to mix passing RBI and the Subtarget; should we pass
|
|
|
|
// TII/TRI as well?
|
2016-10-11 05:50:00 +08:00
|
|
|
GISel->InstSelector.reset(new AArch64InstructionSelector(*this, *I, *RBI));
|
2016-07-27 22:31:55 +08:00
|
|
|
|
|
|
|
GISel->RegBankInfo.reset(RBI);
|
2016-04-07 01:26:03 +08:00
|
|
|
#endif
|
2016-04-15 01:45:38 +08:00
|
|
|
I->setGISelAccessor(*GISel);
|
2014-10-06 14:45:36 +08:00
|
|
|
}
|
|
|
|
return I.get();
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
void AArch64leTargetMachine::anchor() { }
|
2014-04-23 18:26:40 +08:00
|
|
|
|
2015-06-12 03:41:26 +08:00
|
|
|
AArch64leTargetMachine::AArch64leTargetMachine(
|
|
|
|
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
|
2016-05-19 06:04:49 +08:00
|
|
|
const TargetOptions &Options, Optional<Reloc::Model> RM,
|
|
|
|
CodeModel::Model CM, CodeGenOpt::Level OL)
|
2015-06-12 03:41:26 +08:00
|
|
|
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
2014-04-23 18:26:40 +08:00
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
void AArch64beTargetMachine::anchor() { }
|
2014-04-23 18:26:40 +08:00
|
|
|
|
2015-06-12 03:41:26 +08:00
|
|
|
AArch64beTargetMachine::AArch64beTargetMachine(
|
|
|
|
const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
|
2016-05-19 06:04:49 +08:00
|
|
|
const TargetOptions &Options, Optional<Reloc::Model> RM,
|
|
|
|
CodeModel::Model CM, CodeGenOpt::Level OL)
|
2015-06-12 03:41:26 +08:00
|
|
|
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
|
2014-04-23 18:26:40 +08:00
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
namespace {
|
2017-01-06 08:30:53 +08:00
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
/// AArch64 Code Generator Pass Configuration Options.
|
|
|
|
class AArch64PassConfig : public TargetPassConfig {
|
2014-03-29 18:18:08 +08:00
|
|
|
public:
|
2014-05-24 20:50:23 +08:00
|
|
|
AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
|
2014-09-13 01:40:39 +08:00
|
|
|
: TargetPassConfig(TM, PM) {
|
2014-09-13 06:17:28 +08:00
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None)
|
|
|
|
substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
|
2014-09-13 01:40:39 +08:00
|
|
|
}
|
2014-03-29 18:18:08 +08:00
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
AArch64TargetMachine &getAArch64TargetMachine() const {
|
|
|
|
return getTM<AArch64TargetMachine>();
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
2016-11-29 04:11:54 +08:00
|
|
|
ScheduleDAGInstrs *
|
|
|
|
createMachineScheduler(MachineSchedContext *C) const override {
|
|
|
|
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
|
|
|
|
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
|
|
|
|
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
|
2017-02-01 10:54:34 +08:00
|
|
|
DAG->addMutation(createAArch64MacroFusionDAGMutation());
|
2016-11-29 04:11:54 +08:00
|
|
|
return DAG;
|
|
|
|
}
|
|
|
|
|
2017-02-01 10:54:42 +08:00
|
|
|
ScheduleDAGInstrs *
|
|
|
|
createPostMachineScheduler(MachineSchedContext *C) const override {
|
|
|
|
const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
|
|
|
|
if (ST.hasFuseLiterals()) {
|
|
|
|
// Run the Macro Fusion after RA again since literals are expanded from
|
|
|
|
// pseudos then (v. addPreSched2()).
|
|
|
|
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
|
|
|
|
DAG->addMutation(createAArch64MacroFusionDAGMutation());
|
|
|
|
return DAG;
|
|
|
|
}
|
|
|
|
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
|
2014-05-30 18:09:59 +08:00
|
|
|
void addIRPasses() override;
|
2014-04-29 15:58:25 +08:00
|
|
|
bool addPreISel() override;
|
|
|
|
bool addInstSelector() override;
|
2016-02-12 03:35:06 +08:00
|
|
|
#ifdef LLVM_BUILD_GLOBAL_ISEL
|
|
|
|
bool addIRTranslator() override;
|
2016-07-23 04:03:43 +08:00
|
|
|
bool addLegalizeMachineIR() override;
|
2016-04-08 04:27:33 +08:00
|
|
|
bool addRegBankSelect() override;
|
2016-07-27 22:31:55 +08:00
|
|
|
bool addGlobalInstructionSelect() override;
|
2016-02-12 03:35:06 +08:00
|
|
|
#endif
|
2014-04-29 15:58:25 +08:00
|
|
|
bool addILPOpts() override;
|
2014-12-12 05:26:47 +08:00
|
|
|
void addPreRegAlloc() override;
|
|
|
|
void addPostRegAlloc() override;
|
|
|
|
void addPreSched2() override;
|
|
|
|
void addPreEmitPass() override;
|
2017-03-02 07:33:08 +08:00
|
|
|
|
|
|
|
bool isGlobalISelEnabled() const override;
|
2014-03-29 18:18:08 +08:00
|
|
|
};
|
2017-01-06 08:30:53 +08:00
|
|
|
|
|
|
|
} // end anonymous namespace
|
2014-03-29 18:18:08 +08:00
|
|
|
|
2015-02-01 21:20:00 +08:00
|
|
|
TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
|
2015-09-17 07:38:13 +08:00
|
|
|
return TargetIRAnalysis([this](const Function &F) {
|
2015-02-01 21:20:00 +08:00
|
|
|
return TargetTransformInfo(AArch64TTIImpl(this, F));
|
|
|
|
});
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
|
|
return new AArch64PassConfig(this, PM);
|
2014-03-29 18:18:08 +08:00
|
|
|
}
|
|
|
|
|
2014-05-30 18:09:59 +08:00
|
|
|
void AArch64PassConfig::addIRPasses() {
|
|
|
|
// Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
|
|
|
|
// ourselves.
|
2014-08-22 05:50:01 +08:00
|
|
|
addPass(createAtomicExpandPass(TM));
|
2014-05-30 18:09:59 +08:00
|
|
|
|
|
|
|
// Cmpxchg instructions are often used with a subsequent comparison to
|
|
|
|
// determine whether it succeeded. We can exploit existing control-flow in
|
|
|
|
// ldrex/strex loops to simplify this, but it needs tidying up.
|
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
|
|
|
|
addPass(createCFGSimplificationPass());
|
|
|
|
|
2016-07-07 07:18:58 +08:00
|
|
|
// Run LoopDataPrefetch
|
2016-03-18 08:27:29 +08:00
|
|
|
//
|
|
|
|
// Run this before LSR to remove the multiplies involved in computing the
|
|
|
|
// pointer values N iterations ahead.
|
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None && EnableLoopDataPrefetch)
|
|
|
|
addPass(createLoopDataPrefetchPass());
|
|
|
|
|
2014-05-30 18:09:59 +08:00
|
|
|
TargetPassConfig::addIRPasses();
|
2014-11-19 14:39:53 +08:00
|
|
|
|
[AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses.
E.g. Lower an interleaved load:
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
into:
%ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
%vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
%vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
E.g. Lower an interleaved store:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
into:
%sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
%sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
%sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
Differential Revision: http://reviews.llvm.org/D10533
llvm-svn: 240754
2015-06-26 10:32:07 +08:00
|
|
|
// Match interleaved memory accesses to ldN/stN intrinsics.
|
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None)
|
|
|
|
addPass(createInterleavedAccessPass(TM));
|
|
|
|
|
2014-11-19 14:39:53 +08:00
|
|
|
if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
|
|
|
|
// Call SeparateConstOffsetFromGEP pass to extract constants within indices
|
|
|
|
// and lower a GEP with multiple indices to either arithmetic operations or
|
|
|
|
// multiple GEPs with single index.
|
|
|
|
addPass(createSeparateConstOffsetFromGEPPass(TM, true));
|
|
|
|
// Call EarlyCSE pass to find and remove subexpressions in the lowered
|
|
|
|
// result.
|
|
|
|
addPass(createEarlyCSEPass());
|
|
|
|
// Do loop invariant code motion in case part of the lowered result is
|
|
|
|
// invariant.
|
|
|
|
addPass(createLICMPass());
|
|
|
|
}
|
2014-05-30 18:09:59 +08:00
|
|
|
}
|
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
// Pass Pipeline Configuration
|
2014-05-24 20:50:23 +08:00
|
|
|
bool AArch64PassConfig::addPreISel() {
|
2014-03-29 18:18:08 +08:00
|
|
|
// Run promote constant before global merge, so that the promoted constants
|
|
|
|
// get a chance to be merged
|
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
|
2014-05-24 20:50:23 +08:00
|
|
|
addPass(createAArch64PromoteConstantPass());
|
2015-02-24 03:28:45 +08:00
|
|
|
// FIXME: On AArch64, this depends on the type.
|
|
|
|
// Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
|
|
|
|
// and the offset has to be a multiple of the related size in bytes.
|
2015-06-05 04:39:23 +08:00
|
|
|
if ((TM->getOptLevel() != CodeGenOpt::None &&
|
2015-04-11 08:06:36 +08:00
|
|
|
EnableGlobalMerge == cl::BOU_UNSET) ||
|
2015-06-05 04:39:23 +08:00
|
|
|
EnableGlobalMerge == cl::BOU_TRUE) {
|
|
|
|
bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
|
|
|
|
(EnableGlobalMerge == cl::BOU_UNSET);
|
|
|
|
addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
|
|
|
|
}
|
|
|
|
|
2016-08-01 13:56:57 +08:00
|
|
|
if (TM->getOptLevel() != CodeGenOpt::None && EnableAddressTypePromotion)
|
2014-07-03 02:17:40 +08:00
|
|
|
addPass(createAArch64AddressTypePromotionPass());
|
2014-04-18 04:00:24 +08:00
|
|
|
|
2014-03-29 18:18:08 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
bool AArch64PassConfig::addInstSelector() {
|
|
|
|
addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
|
2014-03-29 18:18:08 +08:00
|
|
|
|
|
|
|
// For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
|
|
|
|
// references to _TLS_MODULE_BASE_ as possible.
|
2015-06-16 23:44:21 +08:00
|
|
|
if (TM->getTargetTriple().isOSBinFormatELF() &&
|
2014-03-29 18:18:08 +08:00
|
|
|
getOptLevel() != CodeGenOpt::None)
|
2014-05-24 20:50:23 +08:00
|
|
|
addPass(createAArch64CleanupLocalDynamicTLSPass());
|
2014-03-29 18:18:08 +08:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-02-12 03:35:06 +08:00
|
|
|
#ifdef LLVM_BUILD_GLOBAL_ISEL
|
|
|
|
bool AArch64PassConfig::addIRTranslator() {
|
|
|
|
addPass(new IRTranslator());
|
|
|
|
return false;
|
|
|
|
}
|
2017-01-06 08:30:53 +08:00
|
|
|
|
2016-07-23 04:03:43 +08:00
|
|
|
bool AArch64PassConfig::addLegalizeMachineIR() {
|
2016-10-15 06:18:18 +08:00
|
|
|
addPass(new Legalizer());
|
2016-07-23 04:03:43 +08:00
|
|
|
return false;
|
|
|
|
}
|
2017-01-06 08:30:53 +08:00
|
|
|
|
2016-04-08 04:27:33 +08:00
|
|
|
bool AArch64PassConfig::addRegBankSelect() {
|
|
|
|
addPass(new RegBankSelect());
|
|
|
|
return false;
|
|
|
|
}
|
2017-01-06 08:30:53 +08:00
|
|
|
|
2016-07-27 22:31:55 +08:00
|
|
|
bool AArch64PassConfig::addGlobalInstructionSelect() {
|
|
|
|
addPass(new InstructionSelect());
|
|
|
|
return false;
|
|
|
|
}
|
2016-02-12 03:35:06 +08:00
|
|
|
#endif
|
|
|
|
|
2017-03-02 07:33:08 +08:00
|
|
|
bool AArch64PassConfig::isGlobalISelEnabled() const {
|
|
|
|
return TM->getOptLevel() <= EnableGlobalISelAtO;
|
|
|
|
}
|
|
|
|
|
2014-05-24 20:50:23 +08:00
|
|
|
bool AArch64PassConfig::addILPOpts() {
|
2014-09-05 10:55:24 +08:00
|
|
|
if (EnableCondOpt)
|
|
|
|
addPass(createAArch64ConditionOptimizerPass());
|
2014-03-29 18:18:08 +08:00
|
|
|
if (EnableCCMP)
|
2014-05-24 20:50:23 +08:00
|
|
|
addPass(createAArch64ConditionalCompares());
|
2014-08-08 05:40:58 +08:00
|
|
|
if (EnableMCR)
|
|
|
|
addPass(&MachineCombinerID);
|
2014-08-06 21:31:32 +08:00
|
|
|
if (EnableEarlyIfConversion)
|
|
|
|
addPass(&EarlyIfConverterID);
|
2014-03-29 18:18:08 +08:00
|
|
|
if (EnableStPairSuppress)
|
2014-05-24 20:50:23 +08:00
|
|
|
addPass(createAArch64StorePairSuppressPass());
|
2016-10-08 20:30:07 +08:00
|
|
|
addPass(createAArch64VectorByElementOptPass());
|
2014-03-29 18:18:08 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-12-12 05:26:47 +08:00
|
|
|
void AArch64PassConfig::addPreRegAlloc() {
|
2016-11-16 11:38:27 +08:00
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// Change dead register definitions to refer to the zero register.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
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addPass(createAArch64DeadRegisterDefinitions());
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2014-03-29 18:18:08 +08:00
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// Use AdvSIMD scalar instructions whenever profitable.
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2014-08-22 02:10:07 +08:00
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if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
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2014-12-12 07:18:03 +08:00
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addPass(createAArch64AdvSIMDScalar());
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2014-08-22 02:10:07 +08:00
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// The AdvSIMD pass may produce copies that can be rewritten to
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// be register coaleascer friendly.
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addPass(&PeepholeOptimizerID);
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}
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2014-03-29 18:18:08 +08:00
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}
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2014-12-12 05:26:47 +08:00
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void AArch64PassConfig::addPostRegAlloc() {
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[AArch64] Add pass to remove redundant copy after RA
Summary:
This change will add a pass to remove unnecessary zero copies in target blocks
of cbz/cbnz instructions. E.g., the copy instruction in the code below can be
removed because the cbz jumps to BB1 when x0 is zero :
BB0:
cbz x0, .BB1
BB1:
mov x0, xzr
Jun
Reviewers: gberry, jmolloy, HaoLiu, MatzeB, mcrosier
Subscribers: mcrosier, mssimpso, haicheng, bmakam, llvm-commits, aemerson, rengolin
Differential Revision: http://reviews.llvm.org/D16203
llvm-svn: 261004
2016-02-17 04:02:39 +08:00
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// Remove redundant copy instructions.
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if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
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addPass(createAArch64RedundantCopyEliminationPass());
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2015-03-04 07:22:40 +08:00
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if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
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2014-08-08 20:33:21 +08:00
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// Improve performance for some FP/SIMD code for A57.
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addPass(createAArch64A57FPLoadBalancing());
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2014-03-29 18:18:08 +08:00
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}
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2014-12-12 05:26:47 +08:00
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void AArch64PassConfig::addPreSched2() {
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2014-03-29 18:18:08 +08:00
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// Expand some pseudo instructions to allow proper scheduling.
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2014-12-12 07:18:03 +08:00
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addPass(createAArch64ExpandPseudoPass());
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2014-03-29 18:18:08 +08:00
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// Use load/store pair instructions when possible.
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2014-05-08 00:41:55 +08:00
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if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
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2014-05-24 20:50:23 +08:00
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addPass(createAArch64LoadStoreOptimizationPass());
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2014-03-29 18:18:08 +08:00
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}
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2014-12-12 05:26:47 +08:00
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void AArch64PassConfig::addPreEmitPass() {
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2014-10-13 18:12:35 +08:00
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if (EnableA53Fix835769)
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2014-12-12 07:18:03 +08:00
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addPass(createAArch64A53Fix835769());
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2014-03-29 18:18:08 +08:00
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// Relax conditional branch instructions if they're otherwise out of
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// range of their destination.
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2016-08-01 13:56:57 +08:00
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if (BranchRelaxation)
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2016-10-06 23:38:53 +08:00
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addPass(&BranchRelaxationPassID);
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2014-04-18 22:54:46 +08:00
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if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
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2015-06-16 23:44:21 +08:00
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TM->getTargetTriple().isOSBinFormatMachO())
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2014-05-24 20:50:23 +08:00
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addPass(createAArch64CollectLOHPass());
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2014-03-29 18:18:08 +08:00
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}
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