2019-04-17 12:52:47 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -newgvn -S %s | FileCheck %s
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; Ensure that loads that bypass memory def-use chains get added as users of the new
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; MemoryDef. Otherwise this test will not pass memory verification because the value
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; of the load will not be reprocessed until verification.
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; ModuleID = 'bugpoint-reduced-simplified.bc'
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source_filename = "bugpoint-output-f242c4f.bc"
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target triple = "x86_64-apple-darwin16.7.0"
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@global = external global i32 #0
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@global.1 = external global i32 #0
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define void @hoge(i32 %arg) {
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; CHECK-LABEL: @hoge(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB2:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: br label [[BB2]]
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; CHECK: bb2:
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; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[ARG:%.*]], [[BB:%.*]] ]
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; CHECK-NEXT: br label [[BB6:%.*]]
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; CHECK: bb3:
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Infer alignment of unmarked loads in IR/bitcode parsing.
For IR generated by a compiler, this is really simple: you just take the
datalayout from the beginning of the file, and apply it to all the IR
later in the file. For optimization testcases that don't care about the
datalayout, this is also really simple: we just use the default
datalayout.
The complexity here comes from the fact that some LLVM tools allow
overriding the datalayout: some tools have an explicit flag for this,
some tools will infer a datalayout based on the code generation target.
Supporting this properly required plumbing through a bunch of new
machinery: we want to allow overriding the datalayout after the
datalayout is parsed from the file, but before we use any information
from it. Therefore, IR/bitcode parsing now has a callback to allow tools
to compute the datalayout at the appropriate time.
Not sure if I covered all the LLVM tools that want to use the callback.
(clang? lli? Misc IR manipulation tools like llvm-link?). But this is at
least enough for all the LLVM regression tests, and IR without a
datalayout is not something frontends should generate.
This change had some sort of weird effects for certain CodeGen
regression tests: if the datalayout is overridden with a datalayout with
a different program or stack address space, we now parse IR based on the
overridden datalayout, instead of the one written in the file (or the
default one, if none is specified). This broke a few AVR tests, and one
AMDGPU test.
Outside the CodeGen tests I mentioned, the test changes are all just
fixing CHECK lines and moving around datalayout lines in weird places.
Differential Revision: https://reviews.llvm.org/D78403
2020-05-15 03:59:45 +08:00
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* @global, align 4, !h !0
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2019-04-17 12:52:47 +08:00
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; CHECK-NEXT: unreachable
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; CHECK: bb6:
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; CHECK-NEXT: store i32 [[TMP]], i32* @global.1, !h !0
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; CHECK-NEXT: br i1 undef, label [[BB7:%.*]], label [[BB1]]
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; CHECK: bb7:
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; CHECK-NEXT: br i1 undef, label [[BB10:%.*]], label [[BB8:%.*]]
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; CHECK: bb8:
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; CHECK-NEXT: br i1 false, label [[BB9:%.*]], label [[BB3:%.*]]
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; CHECK: bb9:
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; CHECK-NEXT: store i8 undef, i8* null
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; CHECK-NEXT: br label [[BB3]]
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; CHECK: bb10:
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; CHECK-NEXT: store i32 0, i32* @global, !h !0
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; CHECK-NEXT: br label [[BB7]]
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;
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bb:
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br label %bb2
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bb1: ; preds = %bb6
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br label %bb2
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bb2: ; preds = %bb1, %bb
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%tmp = phi i32 [ 0, %bb1 ], [ %arg, %bb ]
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br label %bb6
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bb3: ; preds = %bb9, %bb8
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%tmp4 = load i32, i32* @global, !h !0
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%tmp5 = icmp eq i32 %tmp4, 0
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unreachable
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bb6: ; preds = %bb2
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store i32 %tmp, i32* @global.1, !h !0
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br i1 undef, label %bb7, label %bb1
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bb7: ; preds = %bb10, %bb6
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br i1 undef, label %bb10, label %bb8
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bb8: ; preds = %bb7
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br i1 false, label %bb9, label %bb3
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bb9: ; preds = %bb8
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call void @widget()
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br label %bb3
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bb10: ; preds = %bb7
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store i32 0, i32* @global, !h !0
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br label %bb7
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}
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declare void @widget()
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attributes #0 = { align=4 }
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!0 = !{}
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