maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/lib/Target/PowerPC/PPC.td

84 lines
3.2 KiB
TableGen
Raw Normal View History

Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This is the top level entry point for the PowerPC target.
//
//===----------------------------------------------------------------------===//
// Get the target-independent interfaces which we are implementing.
//
include "../Target.td"
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
Rename PowerPC*.td -> PPC*.td llvm-svn: 23740
2005-10-15 07:40:39 +08:00
include "PPCRegisterInfo.td"
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
include "PPCSchedule.td"
Rename PowerPC*.td -> PPC*.td llvm-svn: 23740
2005-10-15 07:40:39 +08:00
include "PPCInstrInfo.td"
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//===----------------------------------------------------------------------===//
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
// PowerPC Subtarget features.
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
def Feature64Bit : SubtargetFeature<"64bit",
"Should 64 bit instructions be used">;
def Feature64BitRegs : SubtargetFeature<"64bitregs",
"Should 64 bit registers be used">;
def FeatureAltivec : SubtargetFeature<"altivec",
"Should Altivec instructions be used">;
def FeatureGPUL : SubtargetFeature<"gpul",
"Should GPUL instructions be used">;
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def FeatureFSqrt : SubtargetFeature<"fsqrt",
"Should the fsqrt instruction be used">;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//===----------------------------------------------------------------------===//
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
// PowerPC chips sets supported.
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
//
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"generic", G3Itineraries, []>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"601", G3Itineraries, []>;
def : Processor<"602", G3Itineraries, []>;
def : Processor<"603", G3Itineraries, []>;
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
def : Processor<"603e", G3Itineraries, []>;
def : Processor<"603ev", G3Itineraries, []>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"604", G3Itineraries, []>;
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
def : Processor<"604e", G3Itineraries, []>;
def : Processor<"620", G3Itineraries, []>;
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"g3", G3Itineraries, []>;
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"750", G3Itineraries, []>;
def : Processor<"970", G5Itineraries,
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
Feature64Bit /*, Feature64BitRegs */]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
def : Processor<"g5", G5Itineraries,
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's to group appropriately and provide cues to maintainers that the lists don't need to be ordered. llvm-svn: 23880
2005-10-22 16:04:24 +08:00
Feature64Bit /*, Feature64BitRegs */]>;
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td llvm-svn: 23738
2005-10-15 07:37:35 +08:00
def PPC : Target {
// Pointers on PPC are 32-bits in size.
let PointerType = i32;
// According to the Mach-O Runtime ABI, these regs are nonvolatile across
// calls
let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
F30, F31, CR2, CR3, CR4, LR];
// Pull in Instruction Info:
let InstructionSet = PowerPCInstrInfo;
}