maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/PowerPC/scavenging.mir

207 lines
5.0 KiB
Plaintext
Raw Normal View History

RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
# RUN: llc -mtriple=ppc64-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s
---
# CHECK-LABEL: name: noscav0
name: noscav0
tracksRegLiveness: true
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: [[REG0:\$r[0-9]+]] = LI 42
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
; CHECK-NEXT: NOP implicit killed [[REG0]]
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
%0 : gprc = LI 42
NOP implicit %0
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: [[REG1:\$r[0-9]+]] = LI 42
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
; CHECK-NEXT: NOP
; CHECK-NEXT: NOP implicit [[REG1]]
; CHECK-NEXT: NOP
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
; CHECK-NEXT: NOP implicit killed [[REG1]]
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
%1 : gprc = LI 42
NOP
NOP implicit %1
NOP
NOP implicit %1
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: [[REG2:\$r[0-9]+]] = LI 42
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
; CHECK-NEXT: NOP implicit [[REG2]]
%2 : gprc = LI 42
NOP implicit %2
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$x0 = IMPLICIT_DEF
$x1 = IMPLICIT_DEF
$x2 = IMPLICIT_DEF
$x3 = IMPLICIT_DEF
$x4 = IMPLICIT_DEF
$x27 = IMPLICIT_DEF
$x28 = IMPLICIT_DEF
$x29 = IMPLICIT_DEF
$x30 = IMPLICIT_DEF
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK-NOT: $x0 = LI 42
; CHECK-NOT: $x1 = LI 42
; CHECK-NOT: $x2 = LI 42
; CHECK-NOT: $x3 = LI 42
; CHECK-NOT: $x4 = LI 42
; CHECK-NOT: $x5 = LI 42
; CHECK-NOT: $x27 = LI 42
; CHECK-NOT: $x28 = LI 42
; CHECK-NOT: $x29 = LI 42
; CHECK-NOT: $x30 = LI 42
; CHECK: [[REG3:\$r[0-9]+]] = LI 42
; CHECK-NEXT: $x5 = IMPLICIT_DEF
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
; CHECK-NEXT: NOP implicit killed [[REG2]]
; CHECK-NEXT: NOP implicit killed [[REG3]]
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
%3 : gprc = LI 42
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$x5 = IMPLICIT_DEF
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
NOP implicit %2
NOP implicit %3
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
NOP implicit $x0
NOP implicit $x1
NOP implicit $x2
NOP implicit $x3
NOP implicit $x4
NOP implicit $x5
NOP implicit $x27
NOP implicit $x28
NOP implicit $x29
NOP implicit $x30
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
...
---
# CHECK-LABEL: name: scav0
name: scav0
tracksRegLiveness: true
stack:
# variable-sized object should be a reason to reserve an emergency spillslot
# in the RegScavenger
- { id: 0, type: variable-sized, offset: -32, alignment: 1 }
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$x0 = IMPLICIT_DEF
$x1 = IMPLICIT_DEF
$x2 = IMPLICIT_DEF
$x3 = IMPLICIT_DEF
$x4 = IMPLICIT_DEF
$x5 = IMPLICIT_DEF
$x6 = IMPLICIT_DEF
$x7 = IMPLICIT_DEF
$x8 = IMPLICIT_DEF
$x9 = IMPLICIT_DEF
$x10 = IMPLICIT_DEF
$x11 = IMPLICIT_DEF
$x12 = IMPLICIT_DEF
$x13 = IMPLICIT_DEF
$x14 = IMPLICIT_DEF
$x15 = IMPLICIT_DEF
$x16 = IMPLICIT_DEF
$x17 = IMPLICIT_DEF
$x18 = IMPLICIT_DEF
$x19 = IMPLICIT_DEF
$x20 = IMPLICIT_DEF
$x21 = IMPLICIT_DEF
$x22 = IMPLICIT_DEF
$x23 = IMPLICIT_DEF
$x24 = IMPLICIT_DEF
$x25 = IMPLICIT_DEF
$x26 = IMPLICIT_DEF
$x27 = IMPLICIT_DEF
$x28 = IMPLICIT_DEF
$x29 = IMPLICIT_DEF
$x30 = IMPLICIT_DEF
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: STD killed [[SPILLEDREG:\$x[0-9]+]]
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
; CHECK: [[SPILLEDREG]] = LI8 42
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
; CHECK: NOP implicit killed [[SPILLEDREG]]
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
; CHECK: [[SPILLEDREG]] = LD
%0 : g8rc = LI8 42
NOP implicit %0
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
NOP implicit $x0
NOP implicit $x1
NOP implicit $x2
NOP implicit $x3
NOP implicit $x4
NOP implicit $x5
NOP implicit $x6
NOP implicit $x7
NOP implicit $x8
NOP implicit $x9
NOP implicit $x10
NOP implicit $x11
NOP implicit $x12
NOP implicit $x13
NOP implicit $x14
NOP implicit $x15
NOP implicit $x16
NOP implicit $x17
NOP implicit $x18
NOP implicit $x19
NOP implicit $x20
NOP implicit $x21
NOP implicit $x22
NOP implicit $x23
NOP implicit $x24
NOP implicit $x25
NOP implicit $x26
NOP implicit $x27
NOP implicit $x28
NOP implicit $x29
NOP implicit $x30
RegisterScavenging: Add ScavengerTest pass This pass allows to run the register scavenging independently of PrologEpilogInserter to allow targeted testing. Also adds some basic register scavenging tests. llvm-svn: 304606
2017-06-03 07:01:42 +08:00
...
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
---
# Check for bug where we would refuse to spill before the first instruction in a
# block.
# CHECK-LABEL: name: spill_at_begin
# CHECK: bb.0:
# CHECK: liveins:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: STD killed [[REG:\$x[0-9]+]]{{.*}}(store 8 into %stack.{{[0-9]+}})
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
# CHECK: [[REG]] = LIS8 0
# CHECK: [[REG]] = ORI8 killed [[REG]], 48
# CHECK: NOP implicit killed [[REG]]
Fixed typos in tests: s/CHEKC/CHECK/ Reviewers: ilya-biryukov Subscribers: nemanjai, javed.absar, jsji, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D58611 llvm-svn: 354785
2019-02-25 21:41:59 +08:00
# CHECK: [[REG]] = LD{{.*}}(load 8 from %stack.{{[0-9]+}})
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
name: spill_at_begin
tracksRegLiveness: true
stack:
# variable-sized object should be a reason to reserve an emergency spillslot
# in the RegScavenger
- { id: 0, type: variable-sized, offset: -32, alignment: 1 }
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
%0 : g8rc = LIS8 0
%1 : g8rc = ORI8 %0, 48
NOP implicit %1
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
NOP implicit $x0
NOP implicit $x1
NOP implicit $x2
NOP implicit $x3
NOP implicit $x4
NOP implicit $x5
NOP implicit $x6
NOP implicit $x7
NOP implicit $x8
NOP implicit $x9
NOP implicit $x10
NOP implicit $x11
NOP implicit $x12
NOP implicit $x13
NOP implicit $x14
NOP implicit $x15
NOP implicit $x16
NOP implicit $x17
NOP implicit $x18
NOP implicit $x19
NOP implicit $x20
NOP implicit $x21
NOP implicit $x22
NOP implicit $x23
NOP implicit $x24
NOP implicit $x25
NOP implicit $x26
NOP implicit $x27
NOP implicit $x28
NOP implicit $x29
NOP implicit $x30
NOP implicit $x31
RegScavenging: Add scavengeRegisterBackwards() Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
2017-06-17 10:08:18 +08:00
...