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llvm-project/llvm/test/CodeGen/PowerPC/pr35688.ll

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[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion Revision 320791 introduced a pass that transforms reg+reg instructions to reg+imm if they're fed by "load immediate". However, it didn't handle out-of-range shifts correctly as reported in PR35688. This patch fixes that and therefore the PR. Furthermore, there was undefined behaviour in the patch where the RHS of an initialization expression was 32 bits and constant `1` was shifted left 32 bits. This was fixed by ensuring the RHS is 64 bits just like the LHS. Differential Revision: https://reviews.llvm.org/D41369 llvm-svn: 321551
2017-12-29 20:22:27 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[LICM/MSSA] Add promotion to scalars by building an AliasSetTracker with MemorySSA. Summary: Experimentally we found that promotion to scalars carries less benefits than sinking and hoisting in LICM. When using MemorySSA, we build an AliasSetTracker on demand in order to reuse the current infrastructure. We only build it if less than AccessCapForMSSAPromotion exist in the loop, a cap that is by default set to 250. This value ensures there are no runtime regressions, and there are small compile time gains for pathological cases. A much lower value (20) was found to yield a single regression in the llvm-test-suite and much higher benefits for compile times. Conservatively we set the current cap to a high value, but we will explore lowering it when MemorySSA is enabled by default. Reviewers: sanjoy, chandlerc Subscribers: nemanjai, jlebar, Prazek, george.burgess.iv, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D56625 llvm-svn: 353339
2019-02-07 04:25:17 +08:00
; RUN: llc -enable-mssa-loop-dependency=false -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion Revision 320791 introduced a pass that transforms reg+reg instructions to reg+imm if they're fed by "load immediate". However, it didn't handle out-of-range shifts correctly as reported in PR35688. This patch fixes that and therefore the PR. Furthermore, there was undefined behaviour in the patch where the RHS of an initialization expression was 32 bits and constant `1` was shifted left 32 bits. This was fixed by ensuring the RHS is 64 bits just like the LHS. Differential Revision: https://reviews.llvm.org/D41369 llvm-svn: 321551
2017-12-29 20:22:27 +08:00
; RUN: FileCheck %s
[LICM/MSSA] Add promotion to scalars by building an AliasSetTracker with MemorySSA. Summary: Experimentally we found that promotion to scalars carries less benefits than sinking and hoisting in LICM. When using MemorySSA, we build an AliasSetTracker on demand in order to reuse the current infrastructure. We only build it if less than AccessCapForMSSAPromotion exist in the loop, a cap that is by default set to 250. This value ensures there are no runtime regressions, and there are small compile time gains for pathological cases. A much lower value (20) was found to yield a single regression in the llvm-test-suite and much higher benefits for compile times. Conservatively we set the current cap to a high value, but we will explore lowering it when MemorySSA is enabled by default. Reviewers: sanjoy, chandlerc Subscribers: nemanjai, jlebar, Prazek, george.burgess.iv, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D56625 llvm-svn: 353339
2019-02-07 04:25:17 +08:00
; RUN: llc -enable-mssa-loop-dependency=true -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
; RUN: FileCheck %s --check-prefix=MSSA
[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion Revision 320791 introduced a pass that transforms reg+reg instructions to reg+imm if they're fed by "load immediate". However, it didn't handle out-of-range shifts correctly as reported in PR35688. This patch fixes that and therefore the PR. Furthermore, there was undefined behaviour in the patch where the RHS of an initialization expression was 32 bits and constant `1` was shifted left 32 bits. This was fixed by ensuring the RHS is 64 bits just like the LHS. Differential Revision: https://reviews.llvm.org/D41369 llvm-svn: 321551
2017-12-29 20:22:27 +08:00
; Function Attrs: nounwind
define void @ec_GFp_nistp256_points_mul() {
; CHECK-LABEL: ec_GFp_nistp256_points_mul:
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not seeing through to the constant in other blocks. Revert this patch while we come up with a better way to handle that. I will try to follow this up with some better tests. llvm-svn: 358113
2019-04-11 02:00:41 +08:00
; CHECK: ld 5, 0(3)
; CHECK: li 3, 127
; CHECK: li 4, 0
; CHECK: subfic 6, 5, 0
; CHECK: subfze 6, 4
; CHECK: sradi 7, 6, 63
; CHECK: srad 6, 6, 3
; CHECK: subfc 5, 5, 7
; CHECK: subfe 5, 4, 6
[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion Revision 320791 introduced a pass that transforms reg+reg instructions to reg+imm if they're fed by "load immediate". However, it didn't handle out-of-range shifts correctly as reported in PR35688. This patch fixes that and therefore the PR. Furthermore, there was undefined behaviour in the patch where the RHS of an initialization expression was 32 bits and constant `1` was shifted left 32 bits. This was fixed by ensuring the RHS is 64 bits just like the LHS. Differential Revision: https://reviews.llvm.org/D41369 llvm-svn: 321551
2017-12-29 20:22:27 +08:00
; CHECK: sradi 5, 5, 63
[LICM/MSSA] Add promotion to scalars by building an AliasSetTracker with MemorySSA. Summary: Experimentally we found that promotion to scalars carries less benefits than sinking and hoisting in LICM. When using MemorySSA, we build an AliasSetTracker on demand in order to reuse the current infrastructure. We only build it if less than AccessCapForMSSAPromotion exist in the loop, a cap that is by default set to 250. This value ensures there are no runtime regressions, and there are small compile time gains for pathological cases. A much lower value (20) was found to yield a single regression in the llvm-test-suite and much higher benefits for compile times. Conservatively we set the current cap to a high value, but we will explore lowering it when MemorySSA is enabled by default. Reviewers: sanjoy, chandlerc Subscribers: nemanjai, jlebar, Prazek, george.burgess.iv, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D56625 llvm-svn: 353339
2019-02-07 04:25:17 +08:00
; With MemorySSA, everything is taken out of the loop by licm.
; Loads and stores to undef are treated as non-aliasing.
; MSSA-LABEL: ec_GFp_nistp256_points_mul
; MSSA: ld 3, 0(3)
; MSSA: li 4, 0
; MSSA: subfic 5, 3, 0
; MSSA: subfze 5, 4
; MSSA: sradi 5, 5, 63
; MSSA: subfc 3, 3, 5
; MSSA: subfe 3, 4, 5
; MSSA: sradi 3, 3, 63
; MSSA: std 3, 0(3)
[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion Revision 320791 introduced a pass that transforms reg+reg instructions to reg+imm if they're fed by "load immediate". However, it didn't handle out-of-range shifts correctly as reported in PR35688. This patch fixes that and therefore the PR. Furthermore, there was undefined behaviour in the patch where the RHS of an initialization expression was 32 bits and constant `1` was shifted left 32 bits. This was fixed by ensuring the RHS is 64 bits just like the LHS. Differential Revision: https://reviews.llvm.org/D41369 llvm-svn: 321551
2017-12-29 20:22:27 +08:00
entry:
br label %fe_cmovznz.exit.i534.i.15
fe_cmovznz.exit.i534.i.15: ; preds = %fe_cmovznz.exit.i534.i.15, %entry
%0 = load i64, i64* undef, align 8
%1 = load i64, i64* undef, align 8
%conv.i69.i.i = zext i64 %0 to i128
%sub.i72.i.i = sub nsw i128 0, %conv.i69.i.i
%conv.i63.i.i = zext i64 %1 to i128
%add.neg.i.i.i = ashr i128 %sub.i72.i.i, 127
%sub.i65.i.i = sub nsw i128 %add.neg.i.i.i, %conv.i63.i.i
%sub.i65.lobit.i.i = ashr i128 %sub.i65.i.i, 127
%conv1.i58.i.i = and i128 %sub.i65.lobit.i.i, 18446744073709551615
%add3.i59.i.i = add nuw nsw i128 %conv1.i58.i.i, 0
%conv4.i60.i.i = trunc i128 %add3.i59.i.i to i64
store i64 %conv4.i60.i.i, i64* undef, align 16
br label %fe_cmovznz.exit.i534.i.15
}
[LICM/MSSA] Add promotion to scalars by building an AliasSetTracker with MemorySSA. Summary: Experimentally we found that promotion to scalars carries less benefits than sinking and hoisting in LICM. When using MemorySSA, we build an AliasSetTracker on demand in order to reuse the current infrastructure. We only build it if less than AccessCapForMSSAPromotion exist in the loop, a cap that is by default set to 250. This value ensures there are no runtime regressions, and there are small compile time gains for pathological cases. A much lower value (20) was found to yield a single regression in the llvm-test-suite and much higher benefits for compile times. Conservatively we set the current cap to a high value, but we will explore lowering it when MemorySSA is enabled by default. Reviewers: sanjoy, chandlerc Subscribers: nemanjai, jlebar, Prazek, george.burgess.iv, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D56625 llvm-svn: 353339
2019-02-07 04:25:17 +08:00