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llvm-project/llvm/test/CodeGen/AArch64/machine-dead-copy.mir

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[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
[MIR] Print on the given output instead of stderr. Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
2016-07-14 04:36:03 +08:00
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
--- |
define i32 @copyprop1(i32 %a, i32 %b) { ret i32 %a }
define i32 @copyprop2(i32 %a, i32 %b) { ret i32 %a }
define i32 @copyprop3(i32 %a, i32 %b) { ret i32 %a }
define i32 @copyprop4(i32 %a, i32 %b) { ret i32 %a }
[MachineCopyPropagation] Handle COPY with overlapping source/dest. MachineCopyPropagation::CopyPropagateBlock has a bunch of special handling for COPY instructions. This handling assumes that COPY instructions do not modify the source of the copy; this is wrong if the COPY destination overlaps the source. To fix the bug, check explicitly for this situation, and fall back to the generic instruction handling. This bug can't happen for most register classes because they don't have this sort of overlap, but there are a few register classes where this is possible. The testcase uses the AArch64 QQQQ register class. Differential Revision: https://reviews.llvm.org/D44911 llvm-svn: 328851
2018-03-30 08:56:03 +08:00
define i32 @copyprop5(i32 %a, i32 %b) { ret i32 %a }
define i32 @copyprop6(i32 %a, i32 %b) { ret i32 %a }
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
declare i32 @foo(i32)
...
---
# The first copy is dead copy which is not used.
# CHECK-LABEL: name: copyprop1
# CHECK: bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK-NOT: $w20 = COPY
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
2016-08-25 09:27:13 +08:00
name: copyprop1
body: |
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $w0, $w1
$w20 = COPY $w1
BL @foo, csr_aarch64_aapcs, implicit $w0, implicit-def $w0
RET_ReallyLR implicit $w0
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
...
---
# The first copy is not a dead copy which is used in the second copy after the
# call.
# CHECK-LABEL: name: copyprop2
# CHECK: bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: $w20 = COPY
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
2016-08-25 09:27:13 +08:00
name: copyprop2
body: |
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $w0, $w1
$w20 = COPY $w1
BL @foo, csr_aarch64_aapcs, implicit $w0, implicit-def $w0
$w0 = COPY $w20
RET_ReallyLR implicit $w0
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
...
---
# Both the first and second copy are dead copies which are not used.
# CHECK-LABEL: name: copyprop3
# CHECK: bb.0:
# CHECK-NOT: COPY
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
2016-08-25 09:27:13 +08:00
name: copyprop3
body: |
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $w0, $w1
$w20 = COPY $w1
BL @foo, csr_aarch64_aapcs, implicit $w0, implicit-def $w0
$w20 = COPY $w0
RET_ReallyLR implicit $w0
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
...
# The second copy is removed as a NOP copy, after then the first copy become
# dead which should be removed as well.
# CHECK-LABEL: name: copyprop4
# CHECK: bb.0:
# CHECK-NOT: COPY
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
2016-08-25 09:27:13 +08:00
name: copyprop4
body: |
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $w0, $w1
$w20 = COPY $w0
$w0 = COPY $w20
BL @foo, csr_aarch64_aapcs, implicit $w0, implicit-def $w0
RET_ReallyLR implicit $w0
[MachineCopyPropagation] Expose more dead copies across instructions with regmasks When encountering instructions with regmasks, instead of cleaning up all the elements in MaybeDeadCopies map, remove only the instructions erased. By keeping more instruction in MaybeDeadCopies, this change will expose more dead copies across instructions with regmasks. llvm-svn: 264462
2016-03-26 05:15:35 +08:00
...
[MachineCopyPropagation] Handle COPY with overlapping source/dest. MachineCopyPropagation::CopyPropagateBlock has a bunch of special handling for COPY instructions. This handling assumes that COPY instructions do not modify the source of the copy; this is wrong if the COPY destination overlaps the source. To fix the bug, check explicitly for this situation, and fall back to the generic instruction handling. This bug can't happen for most register classes because they don't have this sort of overlap, but there are a few register classes where this is possible. The testcase uses the AArch64 QQQQ register class. Differential Revision: https://reviews.llvm.org/D44911 llvm-svn: 328851
2018-03-30 08:56:03 +08:00
# Don't try to erase any COPY which overlaps itself.
# CHECK-LABEL: name: copyprop5
# CHECK: bb.0:
# CHECK: COPY killed $q26_q27_q28_q29
# CHECK: COPY killed $q28_q29_q30_q31
name: copyprop5
body: |
bb.0:
liveins: $q26_q27_q28_q29
$q28_q29_q30_q31 = COPY killed $q26_q27_q28_q29
$q26_q27_q28_q29 = COPY killed $q28_q29_q30_q31
BL @foo, csr_aarch64_aapcs, implicit killed $q26_q27_q28_q29
RET_ReallyLR
...
# Don't try to analyze any COPY which overlaps itself.
# CHECK-LABEL: name: copyprop6
# CHECK: bb.0:
# CHECK: COPY killed $q26_q27_q28_q29
# CHECK: $q30 = COPY $q28
name: copyprop6
body: |
bb.0:
liveins: $q26_q27_q28_q29
$q28_q29_q30_q31 = COPY killed $q26_q27_q28_q29
$q30 = COPY $q28
BL @foo, csr_aarch64_aapcs, implicit killed $q28_q29_q30_q31
RET_ReallyLR
...