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llvm-project/llvm/test/CodeGen/AArch64/fold-constants.ll

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TRUNCATE constant folding - minor fix for rL233224 Fix for test case found by James Molloy - TRUNCATE of constant build vectors can be more simply achieved by simply replacing with a new build vector node with the truncated value type - no need to touch the scalar operands at all. llvm-svn: 235079
2015-04-16 16:21:09 +08:00
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
define i64 @dotests_616() {
; CHECK-LABEL: dotests_616
[DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag. This patch enables combining integer bitcasts of integer build vectors when the new scalar type is legal. I've avoided floating point because the implementation bitcasts float to int along the way and we would need to check the intermediate types for legality Differential Revision: https://reviews.llvm.org/D58884 llvm-svn: 355324
2019-03-05 03:12:16 +08:00
; CHECK: mov x0, xzr
TRUNCATE constant folding - minor fix for rL233224 Fix for test case found by James Molloy - TRUNCATE of constant build vectors can be more simply achieved by simply replacing with a new build vector node with the truncated value type - no need to touch the scalar operands at all. llvm-svn: 235079
2015-04-16 16:21:09 +08:00
; CHECK-NEXT: ret
entry:
%0 = bitcast <2 x i64> zeroinitializer to <8 x i16>
%1 = and <8 x i16> zeroinitializer, %0
%2 = icmp ne <8 x i16> %1, zeroinitializer
%3 = extractelement <8 x i1> %2, i32 2
%vgetq_lane285 = sext i1 %3 to i16
%vset_lane = insertelement <4 x i16> undef, i16 %vgetq_lane285, i32 0
%4 = bitcast <4 x i16> %vset_lane to <1 x i64>
%vget_lane = extractelement <1 x i64> %4, i32 0
ret i64 %vget_lane
}
[DAGCombiner] Fix PR25763 - vector comparison constant folding + sign-extension PR25763 demonstrated an issue with D14683 - vector comparison constant folding only works for i1 results, so we need to split off the sign-extension of the result to the required type. Luckily this can be done with the existing type legalization code. llvm-svn: 255289
2015-12-11 03:47:06 +08:00
; PR25763 - folding constant vector comparisons with sign-extended result
define <8 x i16> @dotests_458() {
[SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks The NewNodesMustHaveLegalTypes flag is set to false at the beginning of CodeGenAndEmitDAG, and set to true after legalizing types. But before calling CodeGenAndEmitDAG we build the DAG for the basic block. So for the first basic block NewNodesMustHaveLegalTypes would be 'false' during the SDAG building, and for all other basic blocks it would be 'true'. This patch sets the flag to false before SDAG building each basic block. Differential Revision: https://reviews.llvm.org/D33435 llvm-svn: 310239
2017-08-07 13:51:14 +08:00
; CHECK-LABEL: .LCPI1_0:
; CHECK: .hword 0 // 0x0
; CHECK-NEXT: .hword 0 // 0x0
; CHECK-NEXT: .hword 65535 // 0xffff
; CHECK-NEXT: .hword 0 // 0x0
; CHECK-NEXT: .hword 0 // 0x0
; CHECK-NEXT: .hword 0 // 0x0
; CHECK-NEXT: .hword 0 // 0x0
; CHECK-NEXT: .hword 0 // 0x0
[DAGCombiner] Fix PR25763 - vector comparison constant folding + sign-extension PR25763 demonstrated an issue with D14683 - vector comparison constant folding only works for i1 results, so we need to split off the sign-extension of the result to the required type. Luckily this can be done with the existing type legalization code. llvm-svn: 255289
2015-12-11 03:47:06 +08:00
; CHECK-LABEL: dotests_458
[SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks The NewNodesMustHaveLegalTypes flag is set to false at the beginning of CodeGenAndEmitDAG, and set to true after legalizing types. But before calling CodeGenAndEmitDAG we build the DAG for the basic block. So for the first basic block NewNodesMustHaveLegalTypes would be 'false' during the SDAG building, and for all other basic blocks it would be 'true'. This patch sets the flag to false before SDAG building each basic block. Differential Revision: https://reviews.llvm.org/D33435 llvm-svn: 310239
2017-08-07 13:51:14 +08:00
; CHECK: adrp x8, .LCPI1_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]
[DAGCombiner] Fix PR25763 - vector comparison constant folding + sign-extension PR25763 demonstrated an issue with D14683 - vector comparison constant folding only works for i1 results, so we need to split off the sign-extension of the result to the required type. Luckily this can be done with the existing type legalization code. llvm-svn: 255289
2015-12-11 03:47:06 +08:00
; CHECK-NEXT: ret
entry:
%vclz_v.i = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> <i8 127, i8 38, i8 -1, i8 -128, i8 127, i8 0, i8 0, i8 0>, i1 false) #6
%vsra_n = lshr <8 x i8> %vclz_v.i, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
%name_6 = or <8 x i8> %vsra_n, <i8 127, i8 -128, i8 -1, i8 67, i8 84, i8 127, i8 -1, i8 0>
%cmp.i603 = icmp slt <8 x i8> %name_6, <i8 -57, i8 -128, i8 127, i8 -128, i8 -1, i8 0, i8 -1, i8 -1>
%vmovl.i4.i = sext <8 x i1> %cmp.i603 to <8 x i16>
ret <8 x i16> %vmovl.i4.i
}
declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1)