maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/WebAssembly/simd-encodings.s

389 lines
9.5 KiB
ArmAsm
Raw Normal View History

[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
# RUN: llvm-mc -show-encoding -triple=wasm32-unkown-unknown -mattr=+sign-ext,+simd128 < %s | FileCheck %s
# CHECK: v128.const 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
# CHECK-SAME: # encoding: [0xfd,0x00,
# CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
# CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
v128.const 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
# CHECK: v128.const 256, 770, 1284, 1798, 2312, 2826, 3340, 3854
# CHECK-SAME: # encoding: [0xfd,0x00,
# CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
# CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
v128.const 256, 770, 1284, 1798, 2312, 2826, 3340, 3854
# TODO(tlively): Fix assembler so v128.const works with 4xi32 and 2xi64
# CHECK: v128.const 0x1.0402p-121, 0x1.0c0a08p-113,
# CHECK-SAME: 0x1.14121p-105, 0x1.1c1a18p-97
# CHECK-SAME: # encoding: [0xfd,0x00,
# CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
# CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
v128.const 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97
# CHECK: v128.const 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783
# CHECK-SAME: # encoding: [0xfd,0x00,
# CHECK-SAME: 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
# CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
v128.const 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783
# CHECK: v128.load 48:p2align=0 # encoding: [0xfd,0x01,0x00,0x30]
v128.load 48
# CHECK: v128.store 48:p2align=0 # encoding: [0xfd,0x02,0x00,0x30]
v128.store 48
# CHECK: i8x16.splat # encoding: [0xfd,0x03]
i8x16.splat
# CHECK: i16x8.splat # encoding: [0xfd,0x04]
i16x8.splat
# CHECK: i32x4.splat # encoding: [0xfd,0x05]
i32x4.splat
# CHECK: i64x2.splat # encoding: [0xfd,0x06]
i64x2.splat
# CHECK: f32x4.splat # encoding: [0xfd,0x07]
f32x4.splat
# CHECK: f64x2.splat # encoding: [0xfd,0x08]
f64x2.splat
# CHECK: i8x16.extract_lane_s 15 # encoding: [0xfd,0x09,0x0f]
i8x16.extract_lane_s 15
# CHECK: i8x16.extract_lane_u 15 # encoding: [0xfd,0x0a,0x0f]
i8x16.extract_lane_u 15
# CHECK: i16x8.extract_lane_s 7 # encoding: [0xfd,0x0b,0x07]
i16x8.extract_lane_s 7
# CHECK: i16x8.extract_lane_u 7 # encoding: [0xfd,0x0c,0x07]
i16x8.extract_lane_u 7
# CHECK: i32x4.extract_lane 3 # encoding: [0xfd,0x0d,0x03]
i32x4.extract_lane 3
# CHECK: i64x2.extract_lane 1 # encoding: [0xfd,0x0e,0x01]
i64x2.extract_lane 1
# CHECK: f32x4.extract_lane 3 # encoding: [0xfd,0x0f,0x03]
f32x4.extract_lane 3
# CHECK: f64x2.extract_lane 1 # encoding: [0xfd,0x10,0x01]
f64x2.extract_lane 1
# CHECK: i8x16.replace_lane 15 # encoding: [0xfd,0x11,0x0f]
i8x16.replace_lane 15
# CHECK: i16x8.replace_lane 7 # encoding: [0xfd,0x12,0x07]
i16x8.replace_lane 7
# CHECK: i32x4.replace_lane 3 # encoding: [0xfd,0x13,0x03]
i32x4.replace_lane 3
# CHECK: i64x2.replace_lane 1 # encoding: [0xfd,0x14,0x01]
i64x2.replace_lane 1
# CHECK: f32x4.replace_lane 3 # encoding: [0xfd,0x15,0x03]
f32x4.replace_lane 3
# CHECK: f64x2.replace_lane 1 # encoding: [0xfd,0x16,0x01]
f64x2.replace_lane 1
# CHECK: v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23,
# CHECK-SAME: 8, 25, 10, 27, 12, 29, 14, 31
# CHECK-SAME: # encoding: [0xfd,0x17,
# CHECK-SAME: 0x00,0x11,0x02,0x13,0x04,0x15,0x06,0x17,
# CHECK-SAME: 0x08,0x19,0x0a,0x1b,0x0c,0x1d,0x0e,0x1f]
v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31
# CHECK: i8x16.add # encoding: [0xfd,0x18]
i8x16.add
# CHECK: i16x8.add # encoding: [0xfd,0x19]
i16x8.add
# CHECK: i32x4.add # encoding: [0xfd,0x1a]
i32x4.add
# CHECK: i64x2.add # encoding: [0xfd,0x1b]
i64x2.add
# CHECK: i8x16.sub # encoding: [0xfd,0x1c]
i8x16.sub
# CHECK: i16x8.sub # encoding: [0xfd,0x1d]
i16x8.sub
# CHECK: i32x4.sub # encoding: [0xfd,0x1e]
i32x4.sub
# CHECK: i64x2.sub # encoding: [0xfd,0x1f]
i64x2.sub
# CHECK: i8x16.mul # encoding: [0xfd,0x20]
i8x16.mul
# CHECK: i16x8.mul # encoding: [0xfd,0x21]
i16x8.mul
# CHECK: i32x4.mul # encoding: [0xfd,0x22]
i32x4.mul
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.neg # encoding: [0xfd,0x24]
[WebAssembly] SIMD neg Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
2018-09-15 06:35:12 +08:00
i8x16.neg
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.neg # encoding: [0xfd,0x25]
[WebAssembly] SIMD neg Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
2018-09-15 06:35:12 +08:00
i16x8.neg
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.neg # encoding: [0xfd,0x26]
[WebAssembly] SIMD neg Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
2018-09-15 06:35:12 +08:00
i32x4.neg
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i64x2.neg # encoding: [0xfd,0x27]
[WebAssembly] SIMD neg Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
2018-09-15 06:35:12 +08:00
i64x2.neg
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.shl # encoding: [0xfd,0x30]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i8x16.shl
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.shl # encoding: [0xfd,0x31]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i16x8.shl
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.shl # encoding: [0xfd,0x32]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i32x4.shl
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i64x2.shl # encoding: [0xfd,0x33]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i64x2.shl
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.shr_s # encoding: [0xfd,0x34]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i8x16.shr_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.shr_u # encoding: [0xfd,0x35]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i8x16.shr_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.shr_s # encoding: [0xfd,0x36]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i16x8.shr_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.shr_u # encoding: [0xfd,0x37]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i16x8.shr_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.shr_s # encoding: [0xfd,0x38]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i32x4.shr_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.shr_u # encoding: [0xfd,0x39]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i32x4.shr_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i64x2.shr_s # encoding: [0xfd,0x3a]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i64x2.shr_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i64x2.shr_u # encoding: [0xfd,0x3b]
[WebAssembly] SIMD shifts Summary: Implement shifts of vectors by i32. Since LLVM defines shifts as binary operations between two vectors, this involves pattern matching on splatted shift operands. For v2i64 shifts any i32 shift operands have to be zero extended in the input and any i64 shift operands have to be wrapped in the output. Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51906 llvm-svn: 342302
2018-09-15 08:45:31 +08:00
i64x2.shr_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: v128.and # encoding: [0xfd,0x3c]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
v128.and
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: v128.or # encoding: [0xfd,0x3d]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
v128.or
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: v128.xor # encoding: [0xfd,0x3e]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
v128.xor
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: v128.not # encoding: [0xfd,0x3f]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
v128.not
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.eq # encoding: [0xfd,0x49]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.eq
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.eq # encoding: [0xfd,0x4a]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.eq
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.eq # encoding: [0xfd,0x4b]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.eq
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.eq # encoding: [0xfd,0x4d]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.eq
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.eq # encoding: [0xfd,0x4e]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.eq
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.ne # encoding: [0xfd,0x4f]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.ne
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.ne # encoding: [0xfd,0x50]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.ne
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.ne # encoding: [0xfd,0x51]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.ne
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.ne # encoding: [0xfd,0x53]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.ne
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.ne # encoding: [0xfd,0x54]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.ne
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.lt_s # encoding: [0xfd,0x55]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.lt_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.lt_u # encoding: [0xfd,0x56]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.lt_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.lt_s # encoding: [0xfd,0x57]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.lt_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.lt_u # encoding: [0xfd,0x58]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.lt_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.lt_s # encoding: [0xfd,0x59]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.lt_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.lt_u # encoding: [0xfd,0x5a]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.lt_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.lt # encoding: [0xfd,0x5d]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.lt
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.lt # encoding: [0xfd,0x5e]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.lt
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.le_s # encoding: [0xfd,0x5f]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.le_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.le_u # encoding: [0xfd,0x60]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.le_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.le_s # encoding: [0xfd,0x61]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.le_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.le_u # encoding: [0xfd,0x62]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.le_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.le_s # encoding: [0xfd,0x63]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.le_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.le_u # encoding: [0xfd,0x64]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.le_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.le # encoding: [0xfd,0x67]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.le
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.le # encoding: [0xfd,0x68]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.le
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.gt_s # encoding: [0xfd,0x69]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.gt_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.gt_u # encoding: [0xfd,0x6a]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.gt_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.gt_s # encoding: [0xfd,0x6b]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.gt_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.gt_u # encoding: [0xfd,0x6c]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.gt_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.gt_s # encoding: [0xfd,0x6d]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.gt_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.gt_u # encoding: [0xfd,0x6e]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.gt_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.gt # encoding: [0xfd,0x71]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.gt
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.gt # encoding: [0xfd,0x72]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.gt
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.ge_s # encoding: [0xfd,0x73]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.ge_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i8x16.ge_u # encoding: [0xfd,0x74]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i8x16.ge_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.ge_s # encoding: [0xfd,0x75]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.ge_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i16x8.ge_u # encoding: [0xfd,0x76]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i16x8.ge_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.ge_s # encoding: [0xfd,0x77]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.ge_s
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: i32x4.ge_u # encoding: [0xfd,0x78]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
i32x4.ge_u
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.ge # encoding: [0xfd,0x7b]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.ge
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.ge # encoding: [0xfd,0x7c]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.ge
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.neg # encoding: [0xfd,0x7d]
[WebAssembly] SIMD neg Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
2018-09-15 06:35:12 +08:00
f32x4.neg
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.neg # encoding: [0xfd,0x7e]
[WebAssembly] SIMD neg Summary: Depends on D52007. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52009 llvm-svn: 342296
2018-09-15 06:35:12 +08:00
f64x2.neg
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.abs # encoding: [0xfd,0x7f]
[WebAssembly] v4f32.abs and v2f64.abs Summary: implement lowering of @llvm.fabs for vector types. Reviewers: aheejin, dschuff Subscribers: llvm-svn: 342513
2018-09-19 05:45:12 +08:00
f32x4.abs
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.abs # encoding: [0xfd,0x80]
[WebAssembly] v4f32.abs and v2f64.abs Summary: implement lowering of @llvm.fabs for vector types. Reviewers: aheejin, dschuff Subscribers: llvm-svn: 342513
2018-09-19 05:45:12 +08:00
f64x2.abs
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.add # encoding: [0xfd,0x85]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.add
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.add # encoding: [0xfd,0x86]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.add
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.sub # encoding: [0xfd,0x87]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.sub
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.sub # encoding: [0xfd,0x88]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.sub
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.div # encoding: [0xfd,0x89]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.div
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.div # encoding: [0xfd,0x8a]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.div
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f32x4.mul # encoding: [0xfd,0x8b]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f32x4.mul
[WebAssembly] Renumber SIMD ops Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
2018-09-20 10:55:28 +08:00
# CHECK: f64x2.mul # encoding: [0xfd,0x8c]
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
f64x2.mul
[WebAssembly] SIMD sqrt Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52387 llvm-svn: 342937
2018-09-25 11:39:28 +08:00
# CHECK: f32x4.sqrt # encoding: [0xfd,0x8d]
f32x4.sqrt
# CHECK: f64x2.sqrt # encoding: [0xfd,0x8e]
f64x2.sqrt
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: f32x4.convert_s/i32x4 # encoding: [0xfd,0x8f]
f32x4.convert_s/i32x4
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: f32x4.convert_u/i32x4 # encoding: [0xfd,0x90]
f32x4.convert_u/i32x4
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: f64x2.convert_s/i64x2 # encoding: [0xfd,0x91]
f64x2.convert_s/i64x2
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: f64x2.convert_u/i64x2 # encoding: [0xfd,0x92]
f64x2.convert_u/i64x2
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: i32x4.trunc_sat_s/f32x4 # encoding: [0xfd,0x93]
i32x4.trunc_sat_s/f32x4
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: i32x4.trunc_sat_u/f32x4 # encoding: [0xfd,0x94]
i32x4.trunc_sat_u/f32x4
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: i64x2.trunc_sat_s/f64x2 # encoding: [0xfd,0x95]
i64x2.trunc_sat_s/f64x2
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly] Restore slashes in SIMD conversion names Summary: Depends on D52372 and D52442. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52512 llvm-svn: 343558
2018-10-02 09:52:21 +08:00
# CHECK: i64x2.trunc_sat_u/f64x2 # encoding: [0xfd,0x96]
i64x2.trunc_sat_u/f64x2
[WebAssembly] SIMD conversions Summary: Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to int conversions produce poison values if their arguments are out of the convertible range, so a future CL will have to add an LLVM intrinsic to make the saturating behavior of this conversion usable. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52372 llvm-svn: 343052
2018-09-26 08:34:36 +08:00
[WebAssembly][NFC] Move SIMD encoding tests to dedicated file Summary: This change makes the tests more focused and avoids problematic interactions between the testing modes and instruction encoding. This change also allows the other tests to use less verbose output and stricter checks. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52007 llvm-svn: 342287
2018-09-15 05:21:42 +08:00
end_function